Datasheet

DS90C363, DS90CF364
SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams (continued)
Figure 21. Receiver LVDS Input Strobe Position
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
ISI is dependent on interconnect length; may be zero.
Figure 22. Receiver LVDS Input Skew Margin
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