Datasheet

DS90CF363B

SNLS180D –JULY 2004–REVISED APRIL 2013

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Transmitter Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 )

(1)

f = 40 −0.25 0 +0.25 ns

MHz

TPPos1 Transmitter Output Pulse Position for Bit 1 3.32 3.57 3.82 ns

TPPos2 Transmitter Output Pulse Position for Bit 2 6.89 7.14 7.39 ns

TPPos3 Transmitter Output Pulse Position for Bit 3 10.46 10.71 10.96 ns

TPPos4 Transmitter Output Pulse Position for Bit 4 14.04 14.29 14.54 ns

TPPos5 Transmitter Output Pulse Position for Bit 5 17.61 17.86 18.11 ns

TPPos6 Transmitter Output Pulse Position for Bit 6 21.18 21.43 21.68 ns

TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 )

(1)

f = −0.45 0 +0.45 ns

25MHz

TPPos1 Transmitter Output Pulse Position for Bit 1 5.26 5.71 6.16 ns

TPPos2 Transmitter Output Pulse Position for Bit 2 10.98 11.43 11.88 ns

TPPos3 Transmitter Output Pulse Position for Bit 3 16.69 17.14 17.59 ns

TPPos4 Transmitter Output Pulse Position for Bit 4 22.41 22.86 23.31 ns

TPPos5 Transmitter Output Pulse Position for Bit 5 28.12 28.57 29.02 ns

TPPos6 Transmitter Output Pulse Position for Bit 6 33.84 34.29 34.74 ns

TSTC TxIN Setup to TxCLK IN (Figure 7 ) 2.5 ns

THTC TxIN Hold to TxCLK IN (Figure 7 ) 0.5 ns

TCCD TxCLK IN to TxCLK OUT Delay (Figure 8 ) 50% duty cycle input clock is assumed, T 3.011 6.082 ns

= −10°C, and 65MHz for " Min ", T

= 70°C, and 25MHz for " Max ", V

= 3.6V

SSCG Spread Spectrum Clock support; Modulation frequency with a linear f = 25 100KHz ±

profile

(2)

MHz 2.5%/−5%

f = 40 100KHz ±

MHz 2.5%/−5%

f = 65 100KHz ±

MHz 2.5%/−5%

TPLLS Transmitter Phase Lock Loop Set (Figure 9 ) 10 ms

TPDD Transmitter Power Down Delay (Figure 11 ) 100 ns

(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the

performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.

AC Timing Diagrams

Figure 2. “Worst Case” Test Pattern

Product Folder Links: DS90CF363B