Datasheet

DS90C387, DS90CF388
www.ti.com SNLS012H –MAY 2000–REVISED APRIL 2013
Electrical Characteristics
(1)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current, C
L
= 8 pF, f = 40MHz 125 160 mA
Worst Case Worst Case Pattern
f = 65 MHz 200 250 mA
(Figure 1 and Figure 4),
f = 85 MHz 240 275 mA
DUAL (48-bit RGB),
BAL=High (enabled)
f = 112 MHz 250 300 mA
ICCRG Receiver Support Current, C
L
= 8 pF, f = 40MHz 60 95 mA
16 Grayscale 16 Grayscale Pattern
f = 65 MHz 95 125 mA
(Figure 2 and Figure 4),
f = 85 MHz 115 150 mA
DUAL (48-bit RGB),
BAL=High (enabled)
f = 112 MHz 150 270 mA
ICCRZ Receiver Supply Current, PD = Low 255 300 µA
Power Down Receiver Outputs stay low during Powerdown
mode
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Unit
TCIT TxCLK IN Transition Time (Figure 5) DUAL=Gnd or Vcc 1.0 2.0 3.0 ns
DUAL=1/2Vcc 1.0 1.5 1.7 ns
TCIP TxCLK IN Period (Figure 6) DUAL=Gnd or Vcc 8.928 T 30.77 ns
DUAL=1/2Vcc 5.88 15.38 ns
TCIH TxCLK in High Time (Figure 6) 0.35T 0.5T 0.65T ns
TCIL TxCLK in Low Time (Figure 6) 0.35T 0.5T 0.65T ns
TXIT TxIN Transition Time 1.5 6.0 ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Unit
LLHT LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V (disabled) 0.14 0.7 ns
LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.6 ns
LHLT LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V (disabled) 0.16 0.8 ns
LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.7 ns
TBIT Transmitter Output Bit Width DUAL=Gnd or Vcc 1/7 TCIP ns
DUAL=1/2Vcc 2/7 TCIP ns
TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70 MHz −250 0 +250 ps
f = 70 to 112 MHz −200 0 +200 ps
TCCS TxOUT Channel to Channel Skew 100 ps
TSTC TxIN Setup to TxCLK IN (Figure 6) 2.7 ns
THTC TxIN Hold to TxCLK IN (Figure 6) 0 ns
TJCC Transmitter Jitter Cycle-to-cycle (Figure 14 and f = 112 MHz 85 100 ps
Figure 15) , DUAL=Vcc
(1)
f = 85 MHz 60 75 ps
f = 65 MHz 70 80 ps
f = 56 MHz 100 120 ps
f = 32.5 MHz 75 110 ps
TPLLS Transmitter Phase Lock Loop Set (Figure 8) 10 ms
(1) The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is
measured with a cycle-to-cycle jitter of ±3ns applied to the input clock signal while data inputs are switching (see Figure 14 and
Figure 15). A jitter event of 3ns, represents worse case jump in the clock edge from most graphics VGA chips currently available. This
parameter is used when calculating system margin as described in AN-1059 (SNLA050).
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