Datasheet

PLL
8
8
8
8
8
8
8
8
8
8
8
8
PLL
TTL PARALLEL
-
TO
-
LVDS
LVDS
-
TO
-
TTL PARALLEL
DS90C387VJD DS90CF388VJD
DATA (LVDS)
(280 to 672 Mbit/s
On Each LVDS
Channel)
CLOCK (LVDS)
(40 to 112 MHz)
CMOS/TTL OUTPUTS
RED1
GRN1
BLU1
RED2
GRN2
BLU2
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
FPSHIFT OUT
(40 to 112 MHz)
POWER DOWN
RED1
GRN1
BLU1
RED2
GRN2
BLU2
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
FPSHIFT IN
(TRANSMIT CLOCK IN)
(40 to 112 MHz)
CMOS/TTL INPUTS
POWER DOWN
8
8
8
8
8
8
PLL
TTL OUTPUT LATCH
CMOS/TTL OUTPUTS
DESKEW
DATA DE
-
SERIALIZER
/
DC BALANCE
RED1
GRN1
BLU1
RED2
GRN2
BLU2
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
SHFCLKOUT
(40 to 112 MHz)
POWER DOWN
A0
A1
A2
A3
A4
A5
A6
A7
CLK
DS90C387, DS90CF388
SNLS012H –MAY 2000–REVISED APRIL 2013 www.ti.com
Transmitter Block Diagram
Receiver Block Diagram
Generalized Block Diagram
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Product Folder Links: DS90C387 DS90CF388