Datasheet

DS90CF388A Pin Descriptions — FPD Link Receiver

Pin Name I/O No. Description

AnP I 8 Positive LVDS differential data inputs.

AnM I 8 Negative LVDS differential data inputs.

Rn, Gn, Bn,

DE, HSYNC,

VSYNC

O 51 TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3

control lines — HSYNC (LP), VSYNC (FLM), DE (Data Enable).

RxCLK INP I 1 Positive LVDS differential clock input.

RxCLK INM I 1 Negative LVDS differential clock input.

RxCLK OUT O 1 TTL level clock output. The falling edge acts as data strobe.

R_FDE I 1 Programmable control (DE) strobe select. Tied high for data active when DE

is high. (Note 10)

PLLSEL I 1 PLL range select. This pin must be tied to V

for auto-range. NC or tied to

Ground is reserved for future use. Typical shift point is between 55 and 68

MHz. (Notes 10, 11)

I 1 TTL level input. When asserted (low input) the receiver data outputs are low

and clock output is high. (Note 10)

STOPCLK O 1 Indicates receiver clock input signal is not present with a logic high. With a

clock input present, a low logic is indicated.

I 6 Power supply pins for TTL outputs and digital circuitry.

GND I 10 Ground pins for TTL outputs and digital circuitry

PLLV

I 1 Power supply for PLL circuitry.

PLLGND I 2 Ground pin for PLL circuitry.

LVDSV

I 2 Power supply pin for LVDS inputs.

LVDSGND I 3 Ground pins for LVDS inputs.

CNTLE,

CNTLF

2 No Connect. Make NO Connection to these pins - leave these pins open, do

not tie to ground or V

DS90C387A/DS90CF388A