Datasheet

DS90C385A
www.ti.com SNLS167K –MARCH 2004–REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Unit
SSCG Spread Spectrum Clock support; Modulation frequency f = 25 MHz 100kHz
with a linear profile.
(2)
±2.5%/-5%
f = 40 MHz 100kHz
±2.5%/-5%
f = 65 MHz 100kHz
±2.5%/-5%
f = 87.5 MHz 100kHz
±2.5%/-5%
TPLLS Transmitter Phase Lock Loop Set (Figure 10) 10 ms
TPDD Transmitter Power Down Delay (Figure 12) 100 ns
(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLKOUT- pins.
AC Timing Diagrams
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
B. Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Figure 2. “Worst Case" Test Pattern
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