Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - drivers FPD-Link, LVDS 5/0 TSSOP 56

DS90C385A

www.ti.com

SNLS167K –MARCH 2004–REVISED APRIL 2013

+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz

Check for Samples: DS90C385A

FEATURES

DESCRIPTION

The DS90C385A is a pin to pin compatible

• Pin-to-Pin Compatible to DS90C383,

replacement for DS90C383, DS90C383A and

DS90C383A and DS90C385

DS90C385. The DS90C385A has additional features

• No Special Start-Up Sequence Required

and improvements making it an ideal replacement for

between Clock/Data and /PD Pins. Input

DS90C383, DS90C383A and DS90C385. family of

Signals (Clock and Data) can be Applied Either

LVDS Transmitters.

Before or After the Device is Powered.

The DS90C385A transmitter converts 28 bits of

• Support Spread Spectrum Clocking up to

LVCMOS/LVTTL data into four LVDS (Low Voltage

100kHz Frequency Modulation and Deviations

Differential Signaling) data streams. A phase-locked

of ±2.5% Center Spread or -5% Down Spread

transmit clock is transmitted in parallel with the data

streams over the fifth LVDS link. Every cycle of the

• “Input Clock Detection" Feature Will Pull All

transmit clock 28 bits of input data are sampled and

LVDS Pairs to Logic Low When Input Clock is

transmitted. At a transmit clock frequency of 87.5

Missing and When /PD Pin is Logic High

MHz, 24 bits of RGB data and 3 bits of LCD timing

• 18 to 87.5 MHz Shift Clock Support

and control data (FPLINE, FPFRAME, DRDY) are

• Tx Power Consumption < 147 mW (typ) at

transmitted at a rate of 612.5Mbps per LVDS data

channel. Using a 87.5 MHz clock, the data throughput

87.5MHz Grayscale

is 306.25Mbytes/sec. This transmitter can be

• Tx Power-Down Mode < 60 μW (typ)

programmed for Rising edge strobe or Falling edge

• Supports VGA, SVGA, XGA, SXGA(Dual Pixel),

strobe through a dedicated pin. A Rising edge or

SXGA+(Dual Pixel), UXGA(Dual Pixel).

Falling edge strobe transmitter will interoperate with a

Falling edge strobe FPDLink Receiver without any

• Narrow Bus Reduces Cable Size and Cost

translation logic.

• Up to 2.45 Gbps Throughput

This chipset is an ideal means to solve EMI and

• Up to 306.25Megabyte/sec Bandwidth

cable size problems associated with wide, high-speed

• 345 mV (typ) Swing LVDS Devices for Low EMI

TTL interfaces with added Spread Spectrum Clocking

• PLL Requires No External Components

support.

• Compliant to TIA/EIA-644 LVDS standard

• Low Profile 56-lead TSSOP Package

Block Diagram

Figure 1. DS90C385A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
DS90C385A www.ti.com SNLS167K – MARCH 2004 – REVISED APRIL 2013 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz Check for Samples: DS90C385A FEATURES DESCRIPTION • The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90C383A and DS90C385. The DS90C385A has additional features and improvements making it an ideal replacement for DS90C383, DS90C383A and DS90C385. family of LVDS Transmitters.
PAGE 2
DS90C385A SNLS167K – MARCH 2004 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) Supply Voltage (VCC) -0.3V to +4V CMOS/TTL Input Voltage -0.5V to (VCC + 0.3V) LVDS Driver Output Voltage -0.3V to (VCC + 0.
PAGE 3
DS90C385A www.ti.com SNLS167K – MARCH 2004 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage 0 0.8 V VCL Input Clamp Voltage ICL = -18 mA -0.79 -1.5 V IIN Input Current VIN = 0.4V, 2.5V or VCC +1.
PAGE 4
DS90C385A SNLS167K – MARCH 2004 – REVISED APRIL 2013 www.ti.com Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Unit LLHT LVDS Low-to-High Transition Time (Figure 5) 0.75 1.4 ns LHLT LVDS High-to-Low Transition Time (Figure 5) 0.75 1.4 ns TPPos0 Transmitter Output Pulse Position (Figure 13) (1) -0.45 0 +0.45 ns TPPos1 Transmitter Output Pulse Position 5.26 5.71 6.
PAGE 5
DS90C385A www.ti.com SNLS167K – MARCH 2004 – REVISED APRIL 2013 Transmitter Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol SSCG Parameter Spread Spectrum Clock support; Modulation frequency with a linear profile. (2) Min Typ f = 25 MHz 100kHz ±2.5%/-5% f = 40 MHz 100kHz ±2.5%/-5% f = 65 MHz 100kHz ±2.5%/-5% f = 87.5 MHz 100kHz ±2.
PAGE 6
DS90C385A SNLS167K – MARCH 2004 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) A. The 16 grayscale test pattern tests device power consumption for a “typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. B. Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT). C. Recommended pin to signal mapping. Customer may choose to define differently. Figure 3.
PAGE 7
DS90C385A www.ti.com SNLS167K – MARCH 2004 – REVISED APRIL 2013 AC Timing Diagrams (continued) Figure 7. DS90C385A (Transmitter) Setup/Hold and High/Low Times with R_FB pin = GND (Falling Edge Strobe) Figure 8. DS90C385A (Transmitter) Clock In to Clock Out Delay with R_FB pin = VCC Figure 9. DS90C385A (Transmitter) Clock In to Clock Out Delay with R_FB pin = GND Figure 10.
PAGE 8
DS90C385A SNLS167K – MARCH 2004 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) Figure 11. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90C385A Figure 12. Transmitter Power Down Delay Figure 13.
PAGE 9
DS90C385A www.ti.com SNLS167K – MARCH 2004 – REVISED APRIL 2013 DS90C385A DGG (TSSOP) Package Pin Descriptions — FPD Link Transmitter Pin Name I/O No. Description TxIN I 28 LVTTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). TxOUT+ O 4 Positive LVDS differentiaI data output. TxOUT- O 4 Negative LVDS differential data output. TxCLKIN I 1 LVTTL Ievel clock input. Pin name TxCLK IN.
PAGE 10
DS90C385A SNLS167K – MARCH 2004 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION The DS90C385A is backward compatible with the DS90C385, DS90C383A, DS90C383 in TSSOP 56-lead package, and it is a pin-for-pin replacements. This device DS90C385A also features reduced variation of the TCCD parameter which is important for dual pixel applications.
PAGE 11
DS90C385A www.ti.com SNLS167K – MARCH 2004 – REVISED APRIL 2013 Table 1.
PAGE 12
DS90C385A SNLS167K – MARCH 2004 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision J (April 2013) to Revision K • 12 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90C385AMTX TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1 DS90C385AMTX/NOPB TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90C385AMTX TSSOP DGG 56 1000 367.0 367.0 45.0 DS90C385AMTX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.
PAGE 17
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.