Datasheet

DS90C363, DS90CF364
SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams (continued)
Figure 15. DS90CF364 (Receiver) Phase Lock Loop Set Time
Figure 16. Seven Bits of LVDS in One Clock Cycle
Figure 17. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
Figure 18. Transmitter Power Down Delay
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