Datasheet

RCLKOUT
(RFB=1)
Rx IN
RPDL
RCLKIN
|
| || |
V
DIFF
=
0V
1.5V
|
Rx OUT
+
-
+
-
RCLKOUT
RCLK IN
RPDD
PWDNB
1.5V
| | |
Low
Low
V
DD
RCLKOUT
3.15V
RCLK IN
RPLLS
PWDNB
2V
||
2V
DS90C3202
www.ti.com SNLS191D –APRIL 2005–REVISED APRIL 2013
AC Timing Diagrams (continued)
Figure 7. LVCMOS/LVTTL Output Load and Transition Times
Figure 8. Receiver Phase Lock Loop Wake-up Time
Figure 9. Powerdown Delay
Figure 10. Receiver Propagation Delay
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