Datasheet
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
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Receiver Switching Characteristics
(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Condition or Min Typ Max Unit
Reference
CLHT LVCMOS/LVTTL Low-to-High Transition Time, C
L
Rx clock out 1.45 2.10 ns
= 8pF, (Figure 7)
(2)
Rx data out 2.40 3.50 ns
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CHLT LVCMOS/LVTTL High-to-Low Transition Time, C
L
Rx clock out 1.35 2.20 ns
= 8pF, (Figure 7)
(2)
Rx data out 2.40 3.60 ns
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CLHT LVCMOS/LVTTL Low-to-High Transition Time, C
L
Rx clock out 2.45 ns
Programmable = 8pF, (Figure 7)
(2)
Rx data out 3.40 ns
adjustment Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
CHLT LVCMOS/LVTTL High-to-Low Transition Time, C
L
Rx clock out 2.35 ns
Programmable = 8pF, (Figure 7)
(2)
Rx data out 3.40 ns
adjustment Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
RCOP RCLK OUT Period (Figure 13, Figure 14)
(2)
8–135 MHz 7.4 T 125 ns
RCOH RCLK OUT High Time (Figure 13 , Figure 14) Rx clock out 0.4T 0.5T 0.6T ns
RCOL RCLK OUT Low Time (Figure 13 , Figure 14) Rx clock out 0.4T 0.5T 0.6T ns
RSRC RxOUT Setup to RCLK OUT (Figure 13, Figure 14)
(2) (3)
2.60 0.5T ns
Register addr 29d/1dh [2:1]= 00b (Default)
RHRC RxOUT Hold to RCLK OUT (Figure 13 , Figure 14)
(2) (3)
3.60 0.5T ns
Register addr 29d/1dh [2:1]= 00b (Default)
RSRC/RHRC Register addr 29d/1dh [2:1] = 01b, (Figure 15, Figure 16)
(4)
+1UI / -1UI ns
Programmable RSRC increased from default by 1UI
Adjustment RHRC decreased from default by 1UI
Register addr 29d/1dh [2:1] = 10b, (Figure 15 Figure 16)
(4)
-1UI / +1UI ns
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
Register addr 29d/1dh [2:1] = 11b, (Figure 15 Figure 16)
(4)
+2UI / -2UI ns
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
RPLLS Receiver Phase Lock Loop Set (Figure 8) 10 ms
RPDD Receiver Powerdown Delay (Figure 9) 100 ns
RPDL Receiver Propagation Delay — Latency (Figure 10) 4*RCLK ns
RITOL Receiver Input Tolerance V
CM
= 1.25V, 0.25 UI
(Figure 12 Figure 18)
(2) (4)
V
ID
= 350mV
(1) Typical values are given for V
DD
= 3.3V and T
A
= +25°C.
(2) Specification is ensured by characterization.
(3) A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
(4) A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
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