Datasheet

DS90C3202

SNLS191D –APRIL 2005–REVISED APRIL 2013

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The master must generate a “Start” by sending the 7-bit slave address plus a 0 and wait for acknowledge from

DS90C3202. When DS90C3202 acknowledges (the 1st ACK) that the master is calling, the master then sends

the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd

ACK), the master sends the data byte and wait for acknowledge from the slave. When the slave acknowledges

(the 3rd ACK), the master generates a “ Stop”. This completes the “WRITE”.

DS90C3202 Two-Wire Serial Interface Register Table

Address R/W RESET Bit # Description Default Value

0d/0h R PWDN [7:0] Vender ID low byte[7:0] = 05h 0000_0101

1d/1h R PWDN [7:0] Vender ID high byte[15:8] =13h 0001_0011

2d/2h R PWDN [7:0] Device ID low byte[7:0] = 28h 0010_1000

3d/3h R PWDN [7:0] Device ID high byte 15:8] = 67h 0110_0111

4d/4h R PWDN [7:0] Device revision [7:0] = 00h to begin with 0000_0000

5d/5h R PWDN [7:0] Low frequency limit, 8Mhz = 8h 0000_1000

6d/6h R PWDN [7:0] High frequency limit 135Mhz = 87h = 1000_0111

0000_0000_1000_0111

7d/7h R PWDN [7:0] Reserved 0000_0000

8d/8h R PWDN [7:0] Reserved 0000_0000

9d/9h R PWDN [7:0] Reserved 0000_0000

10d/ah R PWDN [7:0] Reserved 0000_0000

11d/bh R PWDN [7:0] Reserved 0000_0000

20d/14h R/W None [7:0] Reserved 0000_0000

21d/15h R/W None [7:0] Reserved 0000_0000

22d/16h R/W None [7:3] Reserved 0000_0000

[2:0] LVDS input skew control for CLK channel,