Datasheet
DS90C3201
FPD-Link
Transmitter
Video
Source
Pixel Data
DE
Clock
VSYNC
HSYNC
Host
(PC, Graphics Board, Video Processor)
Display
(LCD Monitor, LCD TV, Digital TV)
DS90C3202
FPD-Link
Receiver
Digital
Display
Pixel Data
DE
Clock
VSYNC
HSYNC
LVDS Clock
5 Pairs
5 Pairs
LVDS
2-Wire Serial
Interface
LVDS SERIAL-TO-LVTTL PARALLEL
PLL
7
RXOA-/+ RXOA[6:0]
7
RXOB-/+ RXOB[6:0]
7
RXOC-/+ RXOC[6:0]
7
RXOD-/+ RXOD[6:0]
7
RXOE-/+ RXOE[6:0]
7
RXEA-/+ RXEA[6:0]
7
RXEB-/+ RXEB[6:0]
7
RXEC-/+ RXEC[6:0]
7
RXED-/+ RXED[6:0]
7
RXEE-/+ RXEE[6:0]
RCLKIN-/+ RCLKOUT
RFB
PWDNB
MODE0
S2DAT
LVCMOS/LVTTL OUTPUT <69:0>
LVDS INPUT
MODE1
S2CLK
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
Block Diagram
Figure 1. Receiver Block Diagram
Typical Application Diagram
Figure 2. LCD Panel Application Diagram
Functional Description
The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to
transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface
between the digital video processor and the display using a LVDS interface. The DS90C3201 transmitter
serializes 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals
(HSYNC, VSYNC, DE and two user-defined signals) along with clock signal to 10 channels of LVDS signals and
transmits them. The DS90C3202 receiver converts 10 channels of LVDS signals into parallel signals and outputs
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