Datasheet

RXOA,B,C,D,E[6:0]
RCOH
RCOL
RCLK OUT
RCOP
RSRC
RHRC
V
DD
/2 V
DD
/2
V
DD
/2 V
DD
/2
RXEA,B,C,D,E[6:0]
RFB=0
RFB=1
Ideal Strobe Position
t
BIT
(1UI)
Sampling
Window
Ideal Bit Stop
Ideal Bit Start
RITOL
(Left)
2
t
BIT
( )
RITOL
(Right)
RxOUT
RCLKOUT
RFB = 0 RFB = 1
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams (continued)
Figure 11. RFB: LVTTL Level Programmable Strobe Select
RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Please see AN-1217 (SNLA053) for more details.
Cycle-to-cycle jitter is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero.
Figure 12. Receiver Input Tolerance and Sampling Window
Register address 29d/1dh bit [2:1] = 00b
Figure 13. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Disabled
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