Datasheet

Ideal Pulse Width
1 UI = T
CIP
/7
Ideal Bit Start Ideal Bit Stop
TxIN
TxCLK IN
RFB = 0 RFB = 1
TxCLK IN
GND
TCLK OUT
TPDD
PWDNB
1.5V
|
500 mV
|
V
DIFF
= 0V
V
DD
TCLK IN
3.15V
TCLK OUT
TPLLS
PWDNB
1.5V
|
V
DIFF
= 0V
DS90C3201
www.ti.com SNLS192D –APRIL 2005–REVISED APRIL 2013
AC Timing Diagrams (continued)
Figure 10. Phase Lock Loop Set Time
Figure 11. Transmitter Powerdown Delay
Figure 12. LVTLL Input Programmable Strobe Select
Figure 13. Serializer Ideal Pulse Width
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