Datasheet

TxIN [69:0]
TxCLK OUT-
TCIH
TCCD
TCIL
TxCLK IN
TCIP
TSTC
THTC
TxCLK OUT+
V
DD
/2 V
DD
/2
V
DD
/2 V
DD
/2
||
0V
TCITTCIT
80%
80%
20%
20%
0 20 40 60 80 100 120 140 160
FREQUENCY (MHz)
I
CC
(
mA
)
0
50
100
150
200
250
Worst Case
(max)
Worst Case
(typ)
Incr. Pattern
(typ)
Incr. Pattern
(max)
DS90C3201
SNLS192D –APRIL 2005–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams (continued)
Figure 6. Typical and Max ICC with Worst Case and Incremental Test Pattern
Figure 7. LVDS Transition Times
Figure 8. Input Clock Transition Time
Figure 9. Input Setup/Hold Time, High/Low Time, and Clock In to Clock Out Latency
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