Datasheet

DS90C3201
SNLS192D –APRIL 2005–REVISED APRIL 2013 www.ti.com
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Unit
TPPos3 Transmitter Output Pulse Position for bit 3 (6th bit) (Figure 15) 5 UI − 0.2 5 5 UI + 0.2 UI
(1)
TPPos2 Transmitter Output Pulse Position for bit 2 (7th bit) (Figure 15) 6 UI − 0.2 6 6 UI + 0.2 UI
(1)
TSTC Required TxIN Setup to TCLK IN (Figure 9) 1.5 0.69 ns
Register addr 26d/19h bit [2:0] = 000b (Default)
THTC Required TxIN Hold to TCLK IN (Figure 9) 1.5 0.70 ns
Register addr 26d/19h bit [2:0] = 000b (Default)
TSTC/THTC Register addr 26d/19h bit [2:0] = 001b (Figure 14) 0.5/ ns
Programmable Decrease TSTC ~400ps from Default; 1.0
adjustment Increase THTC ~400ps from Default
Register addr 26d/19h bit [2:0] = 010b, 0/ ns
Decrease TSTC ~800ps from default; 1.5
Increase THTC ~800ps from Default
Register addr 26d/19h bit [2:0] = 011b, -0.5/ ns
Decrease TSTC ~1200ps from Default; 2.0
Increase THTC ~1200ps from Default
Register addr 26d/19h bit [2:0] = 111b, 1.5/ ns
Increase TSTC ~800ps from Default; 0
Decrease THTC ~800ps from Default
Register addr 26d/19h bit [2:0] = 110b, 1.4/ ns
Increase TSTC ~600ps from Default; 0
Decrease THTC ~600ps from Default
Register addr 26d/19h bit [2:0] = 101b, 1.1/ ns
Increase TSTC ~400ps from Default; 0.3
Decrease THTC ~400ps from Default
Register addr 26d/19h bit [2:0] = 100b, 0.9/ ns
Increase TSTC ~200ps from Default; 0.5
Decrease THTC ~200ps from Default
TCCD Transmitter TCLKIN (LVTTL) to CLKOUT f = 135 MHz 10 20 ns
(LVDS) Latency
f = 85 MHz
(3)
20 30 ns
(Figure 9)
(2)
f = 65 MHz
(3)
25 40 ns
f = 40 MHz
(3)
40 50 ns
f = 25 MHz
(3)
60 70 ns
f = 8 MHz 180 200 ns
TPPLS Transmitter Phase Lock Loop Set (Figure 10) 10 ms
TPDD Transmitter Powerdown Delay (Figure 11) 100 ns
(2) The typical transmitter TCCD latency is: 1.786*T + 4.19 ns – 2 UI, where T = TCLK IN period.
(3) Specification is ensured by characterization.
Two-Wire Serial Communication Interface
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
SC
S2CLK Clock Frequency 400 kHz
SC:LOW Clock Low Period R
P
= 4.7KΩ, C
L
= 50pF 1.5 us
SC:HIGH Clock High Period R
P
= 4.7KΩ, C
L
= 50pF 0.6 us
SCD:TR S2CLK and S2DAT Rise Time R
P
= 4.7KΩ, C
L
= 50pF 0.3 us
SCD:TF S2CLK and S2DAT Fall Time R
P
= 4.7KΩ, C
L
= 50pF 0.3 us
SU:STA Start Condition Setup Time R
P
= 4.7KΩ, C
L
= 50pF 0.6 us
HD:STA Start Condition Hold Time R
P
= 4.7KΩ, C
L
= 50pF 0.6 us
HD:STO Stop Condition Hold Time R
P
= 4.7KΩ, C
L
= 50pF 0.6 us
SC:SD Clock Falling Edge to Data R
P
= 4.7KΩ, C
L
= 50pF 0 us
SD:SC Data to Clock Rising Edge R
P
= 4.7KΩ, C
L
= 50pF 0.1 us
SCL:SD S2CLK Low to S2DAT Data Valid R
P
= 4.7KΩ, C
L
= 50pF 0.1 0.9 us
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