Datasheet

DS90C3201
www.ti.com SNLS192D –APRIL 2005–REVISED APRIL 2013
Electrical Characteristics
(1) (2) (3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
OS
Offset Voltage (Programmable R
L
= 100Ω, Register addr 28d/1ch 1.0 1.2 1.5 V
register) bit [3:2] (TXE) = 00b,
bit [1:0] (TXO) = 00b, (Default)
R
L
= 100Ω, Register addr 28d/1ch 0.8 1.0 1.2 V
bit [3:2] (TXE) = 01b,
bit [1:0] (TXO) = 01b
R
L
= 100Ω, Register addr 28d/1ch 0.6 0.8 1.0 V
bit [3:2] (TXE) = 10b,
bit [1:0] (TXO) = 10b
ΔV
OS
Change in V
OS
between 50 mV
complimentary output states
I
OS
Output Short Circuit Current V
OUT
= 0V −50 mA
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current, Worst R
L
= 100Ω, f = 8 MHz 20 60 95 mA
Case C
L
= 5pF,
f = 135 MHz 65 150 235 mA
(Figure 4, Figure 6)
(4)
Worst Case Pattern,
Default Register
Settings
ICCTG Transmitter Supply Current, R
L
= 100Ω, f = 8 MHz 15 55 90 mA
Incremental Test Pattern C
L
= 5pF,
f = 135 MHz 40 110 175 mA
(Figure 5 Figure 6)
(5)
Worst Case Pattern,
Default Register
Settings
ICCTZ Transmitter Supply Current, Power PDWNB = Low, 2 mA
Down R
L
= 100Ω, C
L
= 5pF,
Default Register Settings
(4) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
(5) The incremental test pattern tests device power consumption for a “typical” LCD display pattern.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Unit
T
CIT
TCLK IN Transition Time (Figure 8)
(1)
ns
T
CIP
TCLK IN Period (Figure 9) 7.4 T 125.0 ns
T
CIH
TCLK IN High Time (Figure 9) 0.30T
CIP
0.50T
CIP
0.70T
CIP
ns
T
CIL
TCLK IN Low Time (Figure 9) 0.30T
CIP
0.50T
CIP
0.70T
CIP
ns
T
XIT
TxIN Transition Time
(1) (1)
ns
TJIT
RMS
TCLK IN Jitter (RMS) ±200 ps
(1) Less than 5ns or 30% of TCIP, whichever is less.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Unit
LLHT LVDS Low-to-High Transition Time (Figure 7) 0.6 1.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 7) 0.6 1.5 ns
TPPos1 Transmitter Output Pulse Position for bit 1 (1st bit) (Figure 15) −0.2 0 +0.2 UI
(1)
TPPos0 Transmitter Output Pulse Position for bit 0 (2nd bit) (Figure 15) 1 UI − 0.2 1 1 UI + 0.2 UI
(1)
TPPos6 Transmitter Output Pulse Position for bit 6 (3rd bit) (Figure 15) 2 UI − 0.2 2 2 UI + 0.2 UI
(1)
TPPos5 Transmitter Output Pulse Position for bit 5 (4th bit) (Figure 15) 3 UI − 0.2 3 3 UI + 0.2 UI
(1)
TPPos4 Transmitter Output Pulse Position for bit 4 (5th bit) (Figure 15) 4 UI − 0.2 4 4 UI + 0.2 UI
(1)
(1) A Unit Interval (UI) is defined as 1/7th of an ideal clock period (TCIP/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
(Figure 13)
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