Datasheet

DS90C3201
SNLS192D –APRIL 2005–REVISED APRIL 2013 www.ti.com
Table 1. DS90C3201 Two-Wire Serial Interface Register Table (continued)
Address R/W RESET Bit # Description Default Value
28d/1ch R/W PWDN [7] Vod adjustment for TCLK channel 0000_0000
0: TCLK Vod is the same as TXE EVEN BANK (Default)
1: TCLK Vod is the same as TXO ODD BANK
[6] Vos adjustment for TCLK channel
0: TCLK Vos is the same as TXE EVEN BANK (Default)
1: TCLK Vos is the same as TXO ODD BANK
[5] Vod adjustment for TXE EVEN BANK
0: Vod set at 400mV ( Default)
1: Vod set at 250mv
[4] Vod adjustment for TXO ODD BANK
0: Vod set at 400mV ( Default)
1: Vod set at 250mv
[3:2] Vos adjustment for TXE EVEN BANK
11: NA
10: LVDS DR O/P Vos set at 0.8V
01: LVDS DR O/P Vos set at 1.0V
00: LVDS DR O/P Vos set at 1.2V (Default)
[1:0] Vos adjustment for TXO ODD BANK
11: NA
10: LVDS DR O/P Vos set at 0.8V
01: LVDS DR O/P Vos set at 1.0V
00: LVDS DR O/P Vos set at 1.2V (Default)
29d/1dh R/W PWDN [7:5] Reserved 0000_0000
[4] I/O disable control for TXE EVEN BANK channel E,
1: Disable, 0: Enable (Default)
[3] I/O disable control for TXE EVEN BANK channel D,
1: Disable, 0: Enable (Default)
[2] I/O disable control for TXE EVEN BANK channel C,
1: Disable, 0: Enable (Default)
[1] I/O disable control for TXE EVEN BANK channel B,
1: Disable, 0: Enable (Default)
[0] I/O disable control for TXE EVEN BANK channel A,
1: Disable, 0: Enable (Default)
30d/1eh R/W PWDN [7:5] Reserved 0000_0000
[4] I/O disable control for TXO ODD BANK channel E,
1: Disable, 0: Enable (Default)
[3] I/O disable control for TXO ODD BANK channel D,
1: Disable, 0: Enable (Default)
[2] I/O disable control for TXO ODD BANK channel C,
1: Disable, 0: Enable (Default)
[1] I/O disable control for TXO ODD BANK channel B,
1 Disable, 0: Enable (Default)
[0] I/O disable control for TXO ODD BANK channel A,
1: Disable, 0: Enable (Default)
31d/1fh R/W PWDN [7:6] 11: LVDS O/Ps available as long as "NO CLK" is at HIGH 0000_0000
regardless PLL lock or not
10: LVDS O/Ps available after 1K of TCLK cycles detected
& PLL generated strobes are within 0.5UI respect to
REFCLK
01: LVDS O/Ps available after 2K of TCLK cycles detected
00: Default ; LVDS O/Ps available after 1K of TCLK cycles
detected
[5] 0: Default; to select the size of wait counter between 1K or
2K, Default is 1K
[0:4] Reserved
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