Datasheet

Register addr 26d/1ah[2:0]=[111]
Register addr 26d/1ah[2:0]=[110]
CLK
IDS
# 800 ps
Register addr 26d/1ah[2:0]=[000]
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
CLK
IDS
# 600 ps
CLK
IDS
# 400 ps
CLK
IDS
# 200 ps
CLK
IDS
# 400 ps
CLK
IDS
# 800 ps
CLK
IDS
# 1200 ps
Register addr 26d/1ah[2:0]=[101]
Register addr 26d/1ah[2:0]=[100]
Register addr 26d/1ah[2:0]=[001]
Register addr 26d/1ah[2:0]=[010]
Register addr 26d/1ah[2:0]=[011]
Default
Increases Setup # 800 ps
Increases Setup # 600 ps
Increases Setup # 400 ps
Increases Setup # 200 ps
Increases Hold # 400 ps
Increases Hold # 800 ps
Increases Hold # 1200 ps
RFB=0
RFB=1
DS90C3201
SNLS192D –APRIL 2005–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams (continued)
Figure 14. User Programmable Internal Clock Delay Adjustment for Input Data Setup/Hold Optimization
Input Data Sampling Clock (TCLK
IDS
)
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