Datasheet

TCLK
ODD DIN
EVEN DIN
Signal PatternDevice Pin Name
DS90C124, DS90C241
www.ti.com SNLS209L –NOVEMBER 2005–REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver out Clock Period t
RCP
= t
TCP
(1)
RCLK 28.6 200 ns
t
RDC
RCLK Duty Cycle RCLK 45 50 55 %
t
CLH
LVCMOS Low-to-High C
L
= 8 pF ROUT [23:0],
2.5 3.5 ns
Transition Time (lumped load) LOCK, RCLK
(Figure 11)
(1)
t
CHL
LVCMOS High-to-Low
2.5 3.5 ns
Transition Time
t
ROS
ROUT (7:0) Setup Data to RCLK (Figure 15) ROUT [7:0] (0.40)* (29/56)*t
R
ns
(Group 1) t
RCP CP
t
ROH
ROUT (7:0) Hold Data to RCLK (0.40)* (27/56)*t
R
ns
(Group 1) t
RCP CP
t
ROS
ROUT (15:8) Setup Data to RCLK (Figure 15) ROUT [15:8], (0.40)*
0.5*t
RCP
ns
(Group 2) LOCK t
RCP
t
ROH
ROUT (15:8) Hold Data to RCLK (0.40)*
0.5*t
RCP
ns
(Group 2) t
RCP
t
ROS
ROUT (23:16) Setup Data to (Figure 15) ROUT [23:16] (0.40)* (27/56)*t
R
ns
RCLK (Group 3) t
RCP CP
t
ROH
ROUT (23:16) Hold Data to RCLK (0.40)* (29/56)*t
R
ns
(Group 3) t
RCP CP
t
HZR
HIGH to TRI-STATE Delay (Figure 13) ROUT [23:0], 3 10 ns
RCLK, LOCK
t
LZR
LOW to TRI-STATE Delay 3 10 ns
t
ZHR
TRI-STATE to HIGH Delay 3 10 ns
t
ZLR
TRI-STATE to LOW Delay 3 10 ns
t
DD
Deserializer Delay (Figure 12) RCLK [4+(3/56)] [4+(3/56)] ns
T +5.9 T +14
t
DRDL
Deserializer PLL Lock Time from (Figure 14)
(2) (1)
5 MHz 5 50 ms
Powerdown
35 MHz 5 50 ms
RxIN_TOL Receiver INput TOLerance Left, (Figure 16)
(3) (1) (4)
5 MHz–35 MHz
0.25 UI
_L
RxIN_TOL Receiver INput TOLerance Right, (Figure 16)
(3) (1) (4)
5 MHz–35 MHz
0.25 UI
_R
(1) Specification is ensured by characterization and is not tested in production.
(2) The Deserializer PLL lock time (t
DRDL
) may vary depending on input data patterns and the number of transitions within the pattern.
(3) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(4) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
AC TIMING DIAGRAMS AND TEST CIRCUITS
Figure 1. Serializer Input Checkerboard Pattern
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