Datasheet
DS90C124, DS90C241
SNLS209L –NOVEMBER 2005–REVISED APRIL 2013
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Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
Transmit Clock Period (Figure 5) 28.6 T 200 ns
t
TCIH
Transmit Clock High Time 0.4T 0.5T 0.6T ns
t
TCIL
Transmit Clock Low Time 0.4T 0.5T 0.6T ns
t
CLKT
TCLK Input Transition Time (Figure 4) 3 6 ns
t
JIT
TCLK Input Jitter
(1)
33 ps (RMS)
(1) t
JIT
(at BER of 10e-9) specifies the allowable jitter on TCLK. t
JIT
not included in TxOUT_E_O parameter.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
LLHT
LVDS Low-to-High Transition Time R
L
= 100Ω, (Figure 3) 0.6 ns
C
L
= 10 pF to GND
t
LHLT
LVDS High-to-Low Transition Time
0.6 ns
VODSEL = L
t
DIS
DIN (23:0) Setup to TCLK R
L
= 100Ω, 5 ns
C
L
= 10 pF to GND
t
DIH
DIN (23:0) Hold from TCLK
5 ns
(1)
t
HZD
DOUT ± HIGH to TRI-STATE Delay R
L
= 100Ω, 15 ns
C
L
= 10 pF to GND
t
LZD
DOUT ± LOW to TRI-STATE Delay 15 ns
(Figure 6)
(2)
t
ZHD
DOUT ± TRI-STATE to HIGH Delay 200 ns
t
ZLD
DOUT ± TRI-STATE to LOW Delay 200 ns
t
PLD
Serializer PLL Lock Time R
L
= 100Ω, (Figure 7) 10 ms
t
SD
Serializer Delay R
L
= 100Ω, (Figure 8) 3.5T +
3.5T + 10 ns
VODSEL = L, TRFB = H 2.85
R
L
= 100Ω, (Figure 8) 3.5T +
3.5T + 10 ns
VODSEL = L, TRFB = L 2.85
TxOUT_ TxOUT_Eye_Opening 5–35 MHz
0.75 UI
(5)
E_O (respect to ideal) (Figure 9)
(1) (3) (4)
(1) Specification is ensured by characterization and is not tested in production.
(2) When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(3) t
JIT
(at BER of 10e-9) specifies the allowable jitter on TCLK. t
JIT
not included in TxOUT_E_O parameter.
(4) TxOUT_E_O is affected by pre-emphasis value.
(5) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
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