Datasheet
48DIN[19]
47DIN[18]
46DIN[17]
45DIN[16]
44DIN[15]
43
V
SS
IT
42
V
DD
IT
41DIN[14]
40DIN[13]
39DIN[12]
38DIN[11]
37DIN[10]
13
14
15
16
17
18
19
20
21
22
23
24
RESRVD
V
DD
PT1
V
SS
PT1
V
DD
PT0
V
SS
PT0
DEN
DOUT-
DOUT+
V
SS
DR
V
DD
DR
PRE
V
SS
12VODSEL
11TRFB
10TCLK
9TPWDNB
8DCBOFF
7
V
DD
L
6
V
SS
L
5DCAOFF
4DIN[23]
3DIN[22]
2DIN[21]
1DIN[20]
25
26
27
28
29
30
31
32
33
34
35
36
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
V
DD
T
V
SS
T
DIN[5]
DIN[6]
DIN[7]
DIN[8]
DIN[9]
DS90C241
48 PIN TQFP
DS90C124, DS90C241
SNLS209L –NOVEMBER 2005–REVISED APRIL 2013
www.ti.com
DS90C241 Pin Diagram
Serializer - DS90C241
Figure 17. TOP VIEW
DS90C124 Deserializer Pin Descriptions
Pin # Pin Name I/O Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0] LVCMOS_O Receiver LVCMOS level Outputs – Group 1
31-34
13-16, ROUT[15:8] LVCMOS_O Receiver LVCMOS level Outputs – Group 2
21-24
3-6, 9- ROUT[23:16] LVCMOS_O Receiver LVCMOS level Outputs – Group 3
12
18 RCLK LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43 RRFB LVCMOS_I Receiver Clock Edge Select Pin
RRFB = H; R
OUT
LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; R
OUT
LVCMOS Outputs strobed on the Falling Clock Edge.
48 REN LVCMOS_I Receiver Data Enable
REN = H; R
OUT
[23-0] and RCLK are Enabled (ON).
REN = L; R
OUT
[23-0] and RCLK are Disabled (OFF), Receiver R
OUT
[23-0] and RCLK Outputs are
in TRI-STATE, PLL still operational and locked to TCLK.
1 RPWDNB LVCMOS_I Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), R
OUT
[23-0], RCLK, and LOCK are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
17 LOCK LVCMOS_O LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, R
OUT
[23-0] and RCLK are TRI-STATED
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