Datasheet
RIN±
||
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
ROUT [0:23]
RCLK
TRI-STATE
LOCK
}v[šŒ
t
HZR
or t
LZR
t
DRDL
REN
PWDN
2.0V
0.8V
VOH
REN
VOL + 0.5V
VOL
ROUT [23:0]
VOL + 0.5V
t
LZR
500:
VREF = V
DD
/2 for t
ZLR
or t
LZR
,
VOH - 0.5V VOH + 0.5V
t
ZLR
t
HZR
t
ZHR
V
DD
/2 V
DD
/2
VOH
VOL
REN
VREF
+
-
VREF = 0V for t
ZHR
or t
HZR
C
L
= 8pF
23210
||
START
BIT
STOP
BIT
SYMBOL N+3
23210
||
START
BIT
STOP
BIT
SYMBOL N+2
23210
||
START
BIT
STOP
BIT
SYMBOL N+1
23210
||
START
BIT
STOP
BIT
SYMBOL N
RIN0-23
DCA, DCB
RCLK
t
DD
ROUT0-23
SYMBOL N-1 SYMBOL NSYMBOL N-2SYMBOL N-3
DS90C124, DS90C241
www.ti.com
SNLS209L –NOVEMBER 2005–REVISED APRIL 2013
Figure 12. Deserializer Delay
Note: C
L
includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
Figure 13. Deserializer TRI-STATE Test Circuit and Timing
Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DS90C124 DS90C241