Datasheet

DS80PCI800
SNLS334E –APRIL 2011–REVISED MARCH 2012 www.ti.com
Pin Descriptions (continued)
Pin Name Pin Number I/O, Type Pin Description
OUTB_0+, OUTB_0-, 45, 44, 43, 42, O Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
OUTB_1+, OUTB_1-, 40, 39, 38, 37 Compatible with AC coupled CML inputs.
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-,
OUTA_0+, OUTA_0-, 35, 34, 33, 32, O Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
OUTA_1+, OUTA_1-, 31, 30, 29, 28 Compatible with AC coupled CML inputs.
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
Control Pins — Shared (LVCMOS)
ENSMB 48 I, FLOAT, System Management Bus (SMBus) enable pin
LVCMOS Tie 1kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
ENSMB = 1 (SMBUS MODE)
SCL 50 I, LVCMOS ENSMB Master or Slave mode
O, OPEN Drain SMBUS clock input is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
SDA 49 I, LVCMOS, ENSMB Master or Slave mode
O, OPEN Drain The SMBus bi-directional SDA pin is enabled. Data input or open drain
(pull-down only) output.
AD0-AD3 54, 53, 47, 46 I, LVCMOS ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
READ_EN 26 I, LVCMOS When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
ENSMB = 0 (PIN MODE)
EQA0, EQA1, 20, 19, I, 4-LEVEL, EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.
EQB0, EQB1 46, 47 LVCMOS The pins are active only when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3
inputs. See Table 2.
DEMA0, DEMA1, 49, 50, I, 4-LEVEL, DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
DEMB0, DEMB1 53, 54 LVCMOS driver when in Gen1/2 mode. The pins are only active when ENSMB is
de-asserted (low). The 8 channels are organized into two banks. Bank A
is controlled with the DEMA[1:0] pins and bank B is controlled with the
DEMB[1:0] pins. When ENSMB goes high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are converted
to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1
inputs.
See Table 3.
RATE 21 I, 4-LEVEL, RATE control pin selects GEN 1,2 and GEN 3 operating modes.
LVCMOS Tie 1kΩ to GND = GEN 1,2
FLOAT = AUTO Rate Select
Tie 20kΩ to GND = GEN 3 without De-emphasis
Tie 1kΩ to VDD = GEN 3 with De-emphasis
SD_TH 26 I, 4-LEVEL, Controls the internal Signal Detect Threshold.
LVCMOS See Table 5.
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET 22 I, 4-LEVEL, The RXDET pin controls the receiver detect function. Depending on the
LVCMOS input level, a 50Ω or >50kΩ termination to the power rail is enabled.
See Table 4.
RESERVED 23 I, FLOAT Float (leave pin open) = Normal Operation
VDD_SEL 25 I, FLOAT Controls the internal regulator
FLOAT = 2.5V mode
Tie GND = 3.3V mode
PRSNT 52 I, LVCMOS Cable Present Detect input. high when a cable is not present per PCIe
Cabling Spec. 1.0. Puts part into low power mode. When LOW (normal
operation) part is enabled.
See Table 4.
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