Datasheet

46
47
48
49
50
51
52
53
54
43
4241
40
39
38
37
36
22
27
26
25
24
23
21
20
19
45
44
3
4
5
6
7
89
10
1
2
GND
BOTTOM OF PKG
13
14
15
16
17
18
11
12
33
32
3130
29
28
35
34
VDD
VDD
VDD
VDD
100 mils
20 mils
20 mils
VDD
INTERNAL STRIPLINE
EXTERNAL MICROSTRIP
DS80PCI800
www.ti.com SNLS334E –APRIL 2011–REVISED MARCH 2012
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 for additional information on LLP packages.
Figure 7. Typical Routing Options
The graphic shown above depicts different transmission line topologies which can be used in various
combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be
minimized or eliminated by increasing the swell around each hole and providing for a low inductance return
current path. When the via structure is associated with thick backplane PCB, further optimization such as back
drilling is often used to reduce the deterimential high frequency effects of stubs on the signal path.
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