Datasheet
OUTB_0+
OUTB_0-
OUTB_1+
RESERVED
RXDET
ALL_DONE
45
44
43
42
26
25
DAP = GND
OUTB_1-
INB_2+
INB_2-
5
6
7
24
21
20
23
INA_3-
8
INA_0+
INA_0-
VDD
INA_1+
9
10
11
12
INA_1-
EQA0
INA_2+
INA_2-
13
18
14
15
INA_3+
16
17
OUTA_1+
OUTA_1-
EQA1
OUTA_2+
36
34
35
OUTA_2-
OUTA_3+
OUTA_3-
33
31
32
VIN
VDD_SEL
OUTB_3+
OUTB_3-
VDD
41
40
39
RATE
OUTA_0+
OUTA_0-
37
38
INB_0+
INB_0-
INB_1+
INB_1-
OUTB_2-
OUTB_2+
2
4
3
VDD
50
48
47
49
ENSMB
46
51
INB_3+
INB_3-
SMBUS AND CONTROL
30
29
28
SD_TH/READ_EN
52
19
22
PRSNT
27
1
53
54
VDD
VDD
DEMA1/SCL
DEMA0/SDA
DEMB1/AD0
DEMB0/AD1
EQB1/AD2
EQB0/AD3
DS80PCI800
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SNLS334E –APRIL 2011–REVISED MARCH 2012
Pin Diagram
Figure 1. DS80PCI800 Pin Diagram 54 lead
Pin Functions
Pin Descriptions
Pin Name Pin Number I/O, Type Pin Description
Differential High Speed I/O's
INB_0+, INB_0-,INB_1+, 1, 2, 3, 4, I Inverting and non-inverting differential inputs to bank B equalizer. A
INB_1-,INB_2+, INB_2- 5, 6, 7, 8, gated on-chip 50Ω termination resistor connects INB_n+ to VDD and
,INB_3+, INB_3-, INB_n- to VDD when enabled.
INA_0+, INA_0-,INA_1+, 10, 11, 12, 13, I Inverting and non-inverting differential inputs to bank B equalizer. A
INA_1-,INA_2+, INA_2- 15, 16, 17, 18 gated on-chip 50Ω termination resistor connects INA_n+ to VDD and
,INA_3+, INA_3- INA_n- to VDD when enabled.
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