Datasheet

DS80PCI800
www.ti.com SNLS334E –APRIL 2011–REVISED MARCH 2012
Table 9. SMBUS Slave Mode Register Map (continued)
Address Register Name Bit (s) Field Type Default Description
0x1C CH2 - CHB2 7:6 Reserved R/W 0x00 Set bits to 0.
IDLE, RXDET
5 IDLE_AUTO 1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4 IDLE_SEL 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x1D CH2 - CHB2 7:0 EQ Control R/W 0x2F IB2 EQ Control - total of 256 levels.
EQ See Table 2.
0x1E CH2 - CHB2 7 Short Circuit R/W 0xAD 1: Enable the short circuit protection
VOD Protection 0: Disable the short circuit protection
6 RATE_SEL 1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3 Reserved Set bits to default value - 101.
2:0 VOD Control OB2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x1F CH2 - CHB2 7 RXDET STATUS R 0x02 Observation bit for RXDET CH2 - CHB2.
DEM 1: RX = detected
0: RX = not detected
6:5 RATE_DET R Observation bit for RATE_DET CH2 - CHB2.
STATUS 00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W OB2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: DS80PCI800