Datasheet

VDD_SEL
VIN
VDD
VDD
VDD
VDD
VDD
3.3V
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Internal
voltage
regulator
Enable
2.5V
VDD_SEL
VIN
VDD
VDD
VDD
VDD
VDD
Internal
voltage
regulator
Disable
Place 0.1 uF close to VDD Pin
Total capacitance should be 7 0.5 uF
1 uF
10 uF
2.5V
1 uF
10 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Place capcitors close to VDD Pin
open
open
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
3.3V mode 2.5V mode
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
DS80PCI800
www.ti.com SNLS334E –APRIL 2011–REVISED MARCH 2012
Figure 6. 3.3V or 2.5V Supply Connection Diagram
System Information
When using the DS80PCI800 in CPU systems, there are specific signal integrity settings to ensure signal
integrity margin. The settings were achieved with completing extensive testing. Please contact your field
representative for more information regarding the testing completed to achieve these settings.
For tuning the in the downstream direction (from CPU to EP).
• EQ: use the guidelines outlined in table 2.
• De-Emphasis: use the guidelines outlined in table 3.
• VOD: use the guidelines outlined in table 3.
For tuning in the upstream direction (from EP to CPU).
• EQ: use the guidelines outlined in table 2.
• De-Emphasis:
– For trace lengths < 15” set to -3.5 dB
– For trace lengths > 15” set to -6 dB
• VOD: set to 900 mV
Table 2. Equalizer Settings
Level EQA1 EQA0 EQ – 8 bits [7:0] dB at dB at dB at Suggested Use
EQB1 EQB0 1.25 GHz 2.5 GHz 4 GHz
1 0 0 0000 0000 = 0x00 2.1 3.7 4.9 FR4 < 5 inch trace
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