Datasheet
October 2012 SNLU119 3
2. Setup:
2.1. Connect J19: VIN = 3.3V or VDD = 2.5V and GND
For VIN = 3.3V:
Set SW7 pin1 (VDD_SEL) to the ON position (enable internal LDO regulator) and float VDD at J19.
For VDD = 2.5V:
Set SW7 pin1 (VDD_SEL) to the OFF positions (disable internal LDO regulator) and float VIN at J19.
2.2. Set jumper – J20 for VIH connection to VIN or VDD
2.3. Connect 50 Ohm SMA cables to the board
The input signals J1 to J8 can be connected from a pattern generator.
The output signals J9 to J16 can be connected to a scope.
Top 2 – B channel: J1 – IN_B2+, J2 – IN_B2- J9 – OUT_B2+, J10 – OUT_B2-
J3 – IN_B3+, J4 – IN_B3- J11 – OUT_B3+, J12 – OUT_B3-
Bottom 2 – A channel: J5 – IN_A0+, J6 – IN_A0- J13 – OUT_A0+, J14 – OUT_A0-
J7 – IN_A1+, J8 – IN_A1- J15 – OUT_A1+, J16 – OUT_A1-
2.4. Set the control pins for normal operation
SW7 – PRSNT = 0 (enables the device): set switch pin2 to the ON position.
SW9 – RXDET = F (continuous receiver detection): set switches (3-2-1) = (OFF-OFF-OFF).
RXDET = 1 (50 ohm input termination): set switches (3-2-1) = (OFF-OFF-ON).
SW9 – RATE = 1 (GEN3 mode with DEM control): set switches (6-5-4) = (OFF-OFF-ON).
RATE = F (enable rate detection for GEN1,2,3 with DEM control): set switches (6-5-4) to (OFF-OFF-OFF).
RATE = R (GEN3 mode without DEM control): set switches (6-5-4) = (OFF-ON-OFF).
RATE = 0 (GEN1,2 mode with DEM control): set switches (6-5-4) = (ON-OFF-OFF).
SW6 – SD_TH = F (default signal detect threshold level): set switches (3-2-1) = (OFF-OFF-OFF).
SW6 – RES = F (normal operation): set switches (6-5-4) = (OFF-OFF-OFF).
2.5. Set the input equalization level
For external pin mode control of the equalization level:
Set ENSMB = 0 (1kohm to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF).
SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected.
Refer to Table 1 for information on the 3 switch settings for the 4 level input.
Example:
Set EQB[1:0] with SW1 for the B bank of inputs (top 4 inputs of DS80PCI800).
SW1 (6-5-4), (3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQB[1:0] = R,R = 14.6 dB at 4 GHz (level 6).
Set EQA[1:0] with SW8 for the A bank of inputs (bottom 4 inputs of DS80PCI800).
SW8 (6-5-4), (3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQA[1:0] = R,R = 14.6 dB at 4 GHz (level 6).
Table 3: 16 EQ settings when in pin mode
Level
EQA/B[1:0]
SW1 - EQB[1:0]
SW8 - EQA[1:0]
EQ (dB) at 4 GHz
6
5
4
3
2
1
1
0, 0
ON
OFF
OFF
ON
OFF
OFF
4.9
2
0, R
ON
OFF
OFF
OFF
ON
OFF
7.9
3
0, F
ON
OFF
OFF
OFF
OFF
OFF
9.9
4
0, 1
ON
OFF
OFF
OFF
OFF
ON
11.0
5
R, 0
OFF
ON
OFF
ON
OFF
OFF
14.3
6
R, R
OFF
ON
OFF
OFF
ON
OFF
14.6
7
R, F
OFF
ON
OFF
OFF
OFF
OFF
17.0
8
R ,1
OFF
ON
OFF
OFF
OFF
ON
18.5
9
F ,0
OFF
OFF
OFF
ON
OFF
OFF
18.0
10
F, R
OFF
OFF
OFF
OFF
ON
OFF
22.0
11
F, F
OFF
OFF
OFF
OFF
OFF
OFF
24.4
12
F, 1
OFF
OFF
OFF
OFF
OFF
ON
25.8
13
1, 0
OFF
OFF
ON
ON
OFF
OFF
27.4
14
1, R
OFF
OFF
ON
OFF
ON
OFF
29.0
15
1, F
OFF
OFF
ON
OFF
OFF
OFF
31.4
16
1, 1
OFF
OFF
ON
OFF
OFF
ON
32.7