Datasheet

2 DS80PCI800EVK User’s Guide October 2012
Table 1. Switches to set the 4-level input control pins
4 level Input Settings
Setting for 3 pin switches (3-2-1)
0 Tie 1k ohm to GND
ONOFF OFF
R Tie 20k ohm to GND
OFF ONOFF
F FLOAT (open)
OFF OFF OFF
1 Tie 1k ohm to VIH
OFF OFF ON
The following switches are used to set the input condition for the 4-level inputs:
SW1, SW2, SW3, SW5, SW6, SW8, SW9.
There are 3 switches connected to an input signal pin. Each switch when set to the ON position sets the pin to one
of the 4-level setting. The 6 pin switches are assigned similar to the 3 pin switches. The only difference is 2 signal
pins are connected and thus 6-5-4 is for the one signal pin and 3-2-1 is for another signal pin. Please note only 1
switch at the ON position is allowed.
Table 2. Connection and Control Description
Component
Name
Function
J1 to J8
IN_B2+, IN_B2-,
IN_B3+, IN_B3-,
IN_A0+, IN_A0-,
IN_A1+, IN_A1-
High speed differential inputs.
J9 to J16
OUT_B2+, OUT_B2-,
OUT _B3+, OUT_B3-,
OUT _A0+, OUT_A0-,
OUT _A1+, OUT_A1-
High speed differential outputs.
J19 VIN or VDD DC Power VIN or VDD to DS80PCI800SQ
J20 VIN or VDD Jumper VIN or VDD to VIH power
J17 SDA, SCL
Optional SMBUS access pins.
See the datasheet for additional information on SMBUS.
J18 EEPROM Optional socket for EEPROM
SW1 EQB[1:0] or AD[3:2]
PIN MODE EQ control for channel B inputs
SMBUS MODE AD[3:2] device address bits
SW2 ENSMB
ENSMB = LOW PIN MODE
ENSMB = HIGH SMBUS (slave mode)
ENSMB = FLOAT SMBUS (master mode load configuration from EEPROM)
SW3 DEMA[1:0] PIN MODE DE control for channel A outputs
SW4 SDA/SCL “ON” position connects SDA and SCL lines to the device pin.
SW5 DEMB[1:0] or AD[1:0]
PIN MODE DE control for channel B outputs
SMBUS MODE AD[1:0] device address bits
SW6
SD_TH and LPBK -
RES
SD_TH Signal detect threshold level (FLOAT = Default level)
LPBK function for PCI402 and RESERVED for PCI800 (FLOAT = Normal operation)
SW7
VDD_SEL and
PRSNT
VDD_SEL Enable or disable the internal 3.3V to 2.5V regulator.
PRSNT Enable or disable the device (LOW Enables the device)
SW8 EQA[1:0] PIN MODE EQ control for channel A inputs
SW9 RXDET and RATE
RXDET Input internal 50 ohm to VDD terminations
RXDET = F (AUTO RX Detect), RXDET = 1 (50 ohm input termination).
RATE = 0 (GEN1,2) = 2.5G / 5.0G.
RATE = R (GEN3) = 8.0G.
RATE = F (AUTO Detect). The RATE auto detect circuit requires the idle and active
signal which occurs during the link training negotiation.
SW10 READ_EN
ENSMB = FLOAT SMBUS (master mode load configuration from EEPROM)
SW6: SD_TH becomes the READ_EN pin.
To start the loading at power up, set SW6 pin 3 to “ON” position (pull to GND).
To manually control the start, set SW6 pin 1 to “ON” position (pull to VDD) and push
the SW10 button for the high to low transition to start the loading.
When the loading is complete the LED D1 light should turn OFF.