Datasheet

DS64BR401
www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
(1)
Symbol Parameter Conditions Min Typ Max Units
DJ2 Residual Deterministic Jitter Tx Launch Amplitude = 0.8 to
at 6.4 Gbps 1.2 Vp–p, 12 meters (30 AWG),
EQx[1:0] = 1F, DEMx[1:0] = 0 dB, 0.05 0.15 UI
P-P
VOD = 1.0 Vp-p, K28.5,
SD_TH = float,
(5)
DJ3 Residual Deterministic Jitter Tx Launch Amplitude = 0.8 to
at 3.2 Gbps 1.2 Vp–p, 40” 4–mil FR4 trace,
EQx[1:0] = 0F, DEMx[1:0] = 0 dB, 0.05 0.12 UI
P-P
VOD = 1.0 Vp-p, K28.5,
SD_TH = float,
(5)
DJ4 Residual Deterministic Jitter Tx Launch Amplitude = 0.8 to
at 3.2 Gbps 1.2 Vp–p, 12 meters (30 AWG),
EQx[1:0] = 1F, DEMx[1:0] = 0 dB, 0.06 0.16 UI
P-P
VOD = 1.0 Vp-p, K28.5,
SD_TH = float,
(5)
RJ Random Jitter Tx Launch Amplitude = 0.8 to 1.2 Vp–p,
0.5 psrms
Repeating 1100b (D24.3) pattern
DE-EMPHASIS
DJ5 Residual Deterministic Jitter Tx Launch amplitude = 0.8 to
at 6.4 Gbps 1.2 Vp–p, 10” 4–mil FR4 trace,
0.09 0.20 UI
P-P
EQx[1:0] = OFF, DEMx[1:0] = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 1
(5)
DJ6 Residual Deterministic Jitter Tx Launch amplitude = 0.8 to
at 3.2 Gbps 1.2 Vp–p, 20” 4–mil FR4 trace,
0.07 0.18 UI
P-P
EQx[1:0] = OFF, DEMx[1:0] = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 0
(7)
(7) Typical values represent most likely parametric norms at V
DD
= 2.5V, T
A
= 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not verified.
ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ Max Units
SERIAL BUS INTERFACE DC SPECIFICATIONS
V
OL
Data (SDA) Low Level Output I
OL
= 3mA
0.4 V
Voltage
V
IL
Data (SDA), Clock (SCL) Input Low 0.8
V
Voltage
V
IH
Data (SDA), Clock (SCL) Input High 2.1 3.6
V
Voltage
I
PULLUP
Current Through Pull-Up Resistor High Power Specification
4 mA
or Current Source
V
DD
Nominal Bus Voltage 2.375 3.6 V
I
LEAK-Bus
Input Leakage Per Bus Segment
(1)
-200 +200 µA
I
LEAK-Pin
Input Leakage Per Device Pin -15 µA
C
I
Capacitance for SDA and SCL
(1) (2)
10 pF
R
TERM
External Termination Resistance V
DD3.3
,
2000 Ω
pull to V
DD
= 2.5V ± 5% OR 3.3V ±
(1) (2) (3)
10%
V
DD2.5
,
1000 Ω
(1) (2) (3)
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 5
FSMB Bus Operating Frequency
(4)
10 100 kHz
(1) Recommended value. Parameter not tested in production.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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