Datasheet

DS64BR401
SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com
Table 9. SMBus Register Map
Address Register Name Bit (s) Field Type Default Description
0x00 Reset 7:1 Reserved R/W 0x00 Set bits to 0.
0 Reset SMBus Reset
1: Reset registers to default value
0x01 PWDN Channels 7:0 PWDN CHx R/W 0x00 Power Down per Channel
[7]: CHA_3
[6]: CHA_2
[5]: CHA_1
[4]: CHA_0
[3]: CHB_3
[2]: CHB_2
[1]: CHB_1
[0]: CHB_0
00'h = all channels enabled
FF'h = all channels disabled
0x02 PWDN Control 7:1 Reserved R/W 0x00 Set bits to 0.
0 Override PWDN 0: Allow PWDN pin control
1: Block PWDN pin control
0x08 Pin Control Override 7:5 Reserved R/W 0x00 Set bits to 0.
4 Override IDLE 0: Allow IDLE pin control
1: Block IDLE pin control
3 Reserved Set bit to 0.
2 Override RATE 0: Allow RATE pin control
1: Block RATE pin control
1:0 Reserved Set bits to 0.
0x0E CH0 - CHB0 7:6 Reserved R/W 0x00 Set bits to 0.
IDLE RATE Select
5 IDLE auto 0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4 IDLE select 0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2 Reserved Set bits to 0.
1 RATE auto 0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0 RATE select 0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
0x0F CH0 - CHB0 7:6 Reserved R 0x0 Set bits to 0.
EQ Control
5:0 CH0 IB0 EQ R/W 0x20 IB0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ0 EQ1] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
0F = 110001 = 31'h
01 = 111000 = 38'h
1F = 110100 = 34'h
10 = 110101 = 35'h
F0 = 111010 = 3A'h
F1 = 111100 = 3C'h
0x10 CH0 - CHB0 7:6 Reserved R 0x00 Set bit to 0.
VOD Control
5:0 CH0 OB0 VOD R/W 0x03 OB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
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