Datasheet

DS64BR401
SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com
FUNCTIONAL DESCRIPTION
The DS64BR401 is a quad repeater optimized for backplane trace or cable interconnect up to 6.4 Gbps. The
DS64BR401 operates in two modes: Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically
increased per the De-Emphasis table below for improved performance over lossy media. Rate optimization is
also pin controllable, with pin selections for 3 Gbps, 6 Gbps, and auto detect. The receiver electrical idle detect
threshold is also programmable via an optional external resistor on the SD_TH pin.
SMBUS MODE
When in SMBus mode the equalization, de-emphasis are all programmable on a individual lane basis, instead of
grouped by sides as in the pin mode case. Upon assertion of ENSMB the RATE, EQx and DEMx functions revert
to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The
other external control pins remain active unless their respective registers are written to and the appropriate
override bit is set, in which case they are ignored until ENSMB is driven low. On powerup and when ENSMB is
driven low all registers are reset to their default state. If PWDN = 1 is asserted while ENSMB = 1, the registers
retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 24 possible equalization settings. The tables show a typical gain for each gain
stage (GST[4:3]) and boost level (BST[2:0]) combination. When using SMBus mode, the Equalization and De-
Emphasis levels are set using registers. See Table 9 (register map) for more information.
Table 2. Equalization Settings with GST=1 for Pins or SMBus Registers
EQ Setting EQ Gain (dB)
EQ1
(
EQ0
(
Suggested Use
GST[4 BST[2: 1.5 GHz 3.0 GHz
1) 1)
:3] 0]
F F 00 000 0 0 Bypass - Default Setting
01 000 2.0 3.8
01 001 2.6 4.9
1 1 01 010 3.3 5.8 8 inch FR4 (4-mil trace) or < 0.7m (30 AWG)
01 011 3.9 6.8
01 100 4.9 8.2
01 101 5.5 8.9
01 110 6.0 9.4
01 111 6.5 10.0
(1) F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
Table 3. Equalization Settings with GST=2 for Pins or SMBus Registers
EQ Setting EQ Gain (dB)
EQ1
(
EQ0
(
Suggested Use
GST[4 BST[2: 1.5 GHz 3.0 GHz
1) 1)
:3] 0]
0 0 10 000 4.8 9.2 12” FR4 (4-mil trace) or 1m (30 AWG)
F 0 10 001 6.3 11.7 20” FR4 (4-mil trace) or 5m (30 AWG)
10 010 7.6 13.6
10 011 9.1 15.6
F 1 10 100 11.1 18.4 35” FR4 (4-mil trace) or 9m (30 AWG)
0 1 10 101 12.4 20.0 40” FR4 (4-mil trace) or 10m (30 AWG)
10 110 13.4 20.9
(1) F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
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