Datasheet

DS50PCI401
www.ti.com SNLS292J –JUNE 2009–REVISED APRIL 2013
Table 1. Pin Descriptions (continued)
Pin Name Pin Number I/O, Type Pin Description
Control Pins — Both Modes (LVCMOS)
RXDETA,RXDETB 22,23 I, LVCMOS The RXDET pins in combination with the ENRXDET pin controls the
w/internal receiver detect function. Depending on the input level, a 50Ω or >50KΩ
pulldown termination to the power rail is enabled. Refer to Table 6.
PRSNT 52 I, LVCMOS Cable Present Detect input. High when a cable is not present per PCIe
Cabling Spec. 1.0. Puts part into low power mode. When low (normal
operation) part is enabled.
ENRXDET 26 I, LVCMOS Enables pin control of receiver detect function. Pin must be pulled high
w/internal externally for RXDETA/B to function. Controls both A and B sides. Refer
pulldown to Table 6.
TXIDLEA,TXIDLEB 24,25 I, FLOAT, Controls the electrical idle function on corresponding outputs when
LVCMOS enabled. H= electrical Idle, Float=autodetect (Idle on input passed to
output), L=Idle squelch disabled as shown in Table 4.
Analog
SD_TH 27 I, ANALOG Threshold select pin for electrical idle detect threshold. Float pin for
default 130mV DIFF p-p, otherwise connect resistor from SD_TH to GND
to set threshold voltage as shown in Table 5.
Power
VDD 9, 14,36, 41, 51 Power Power supply pins CML/analog.
GND DAP Power Ground pad (DAP - die attach pad).
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