Datasheet

DS50PCI401
SNLS292J –JUNE 2009–REVISED APRIL 2013 www.ti.com
Table 1. Pin Descriptions
Pin Name Pin Number I/O, Type Pin Description
Differential High Speed I/O's
IA_0+, IA_0- , 10, 11 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A
IA_1+, IA_1-, 12, 13 gated on-chip 50Ω termination resistor connects INA_0+ to VDD and
IA_2+, IA_2-, 15, 16 INA_0- to VDD when enabled.
IA_3+, IA_3- 17, 18
OA_0+, OA_0-, 35, 34 O,LPDS Inverting and non-inverting low power differential signal (LPDS) 50Ω
OA_1+, OA_1-, 33, 32 driver outputs with de-emphasis. Compatible with AC coupled CML
OA_2+, OA_2-, 31, 30 inputs.
OA_3+, OA_3- 29, 28
IB_0+, IB_0- , 45, 44 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A
IB_1+, IB_1-, 43, 42 gated on-chip 50Ω termination resistor connects INB_0+ to VDD and
IB_2+, IB_2-, 40, 39 INB_0- to VDD when enabled.
IB_3+, IB_3- 38, 37
OB_0+, OB_0-, 1, 2 O,LPDS Inverting and non-inverting low power differential signal (LPDS) 50Ω
OB_1+, OB_1-, 3, 4 driver outputs with de-emphasis. Compatible with AC coupled CML
OB_2+, OB_2-, 5, 6 inputs.
OB_3+, OB_3- 7, 8
Control Pins — Shared (LVCMOS)
ENSMB 48 I, LVCMOS System Management Bus (SMBus) enable pin.
w/internal When pulled high provide access internal digital registers that are a
pulldown means of auxiliary control for such functions as equalization, de-
emphasis, VOD, rate, and idle detection threshold.
When pulled low, access to the SMBus registers are disabled and
SMBus function pins are used to control the Equalizer and De-Emphasis.
Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND
CONFIGURATION REGISTERS and Electrical Characteristics — Serial
Management Bus Interface for detail information.
ENSMB = 1 (SMBUS MODE)
SCL 50 I, LVCMOS ENSMB = 1
SMBUS clock input pin is enabled. External pull-up resistor maybe
needed. Refer to R
TERM
in the SMBus specification.
SDA 49 I, LVCMOS, ENSMB = 1
O, Open Drain The SMBus bi-directional SDA pin is enabled. Data input or open drain
output. External pull-up resistor is required.
Refer to R
TERM
in the SMBus specification.
AD0-AD3 54, 53, 47, 46 I, LVCMOS ENSMB = 1
w/internal SMBus Slave Address Inputs. In SMBus mode, these pins are the user
pulldown set SMBus slave address inputs. See section — SYSTEM
MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
for additional information.
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1 20, 19 I,FLOAT, EQA/B ,0/1 controls the level of equalization of the A/B sides as shown in
EQB0, EQB1 46, 47 LVCMOS Table 2. The EQA/B pins are active only when ENSMB is de-asserted
(Low). Each of the 4 A/B channels have the same level unless controlled
by the SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane, and the EQB0/B1
pins are converted to SMBUS AD2/AD3 inputs.
DEMA0, DEMA1 49, 50 I,FLOAT, DEMA/B ,0/1 controls the level of de-emphasis of the A/B sides as
DEMB0, DEMB1 53, 54 LVCMOS shown in Table 3. The DEMA/B pins are only active when ENSMB is de-
asserted (Low). Each of the 4 A/B channels have the same level unless
controlled by the SMBus control registers. When ENSMB goes High the
SMBus registers provide independent control of each lane and the DEM
pins are converted to SMBUS AD0/AD1 and SCL/SDA inputs.
RATE 21 I,FLOAT, RATE control pin controls the pulse width of de-emphasis of the output.
LVCMOS A Low forces Gen1 (2.5Gbps), High forces Gen 2 (5Gbps),
Open/Floating the rate is internally detected after each exit from idle and
the pulse width is set appropriately. When ENSMBUS= 1 this pin is
disabled and the RATE function is controlled internally by the SMBUS
registers. Refer to Table 3.
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