Datasheet

-RL
TX-DIFF
(SDD11)
-40
-35
-30
-25
-20
-15
-10
-5
0
0.00
0.50
1.00 1.50 2.00 2.50
S11
Frequency (GHz)
-RL
TX-CM
(S11)
SDD11
Return Loss (dB)
-RL
RX-DIFF
(SDD11)
-40
-35
-30
-25
-20
-15
-10
-5
0
0.00
0.50
1.00 1.50 2.00 2.50
S11
Frequency (GHz)
-RL
RX-CM
(S11)
SDD11
Return Loss (dB)
DS50PCI401
SNLS292J –JUNE 2009–REVISED APRIL 2013 www.ti.com
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS50PCI401 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V
DD
and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01 μF bypass capacitor should be
connected to each V
DD
pin such that the capacitor is placed as close as possible to the DS50PCI401. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
Typical Performance Eye Diagrams and Curves
DS50PCI401 Return Loss
Figure 9. Receiver Return Loss Mask for 5.0 Gbps
Figure 10. Transmitter Return Loss Mask for 5.0 Gbps
28 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI401