Datasheet

DS50PCI401
www.ti.com SNLS292J –JUNE 2009–REVISED APRIL 2013
Table 7. SMBus Register Map (continued)
0x2C CH4 - CHA0 7:6 Reserved R/W 0x20 Set bits to 0.
EQ Control
5:0 CH4 IA0 EQ IA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
0x2D CH4 - CHA0 7 Reserved R/W 0x03 Set bit to 0.
VOD Control
6:0 CH4 OA0 VOD OA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
0x2E CH4 - CHA0 7:0 CH4 OA0 DEM R/W 0x03 OA0 DEM Control
DE Control [7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x2F CH4 - CHA0 7:4 Reserved R/W 0x00 Set bits to 0.
IDLE Threshold
3:0 IDLE threshold De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
0x32 CH5 - CHA1 7:6 Reserved R/W 0x00 Set bits to 0.
IDLE RATE Select
5 IDLE auto 0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4 IDLE select 0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2 Reserved Set bits to 0.
1 RATE auto 0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0 RATE select 0: 2.5 Gbps
1: 5.0 Gbps
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