Datasheet

SP
t
BUF
t
HD:STA
t
LOW
t
R
t
HD:DAT
t
HIGH
t
F
t
SU:DAT
t
SU:STA
ST
SP
t
SU:STO
SCL
SDA
ST
CSA8000B w/TDR module
Supply
PCI401
PCIe EVK board
Gnd
2.5V
OUT+
OUT-
Biasing/
blocking
Bias T
Bias T
Rt
Rl
Rl
Biasing/blocking Circuit
Rt + 2Rl = 98:
Iconnect/PC
DS50PCI401
www.ti.com SNLS292J –JUNE 2009–REVISED APRIL 2013
Figure 6. Input and Output Return Loss Setup
Figure 7. SMBus Timing Parameters
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