Datasheet

DS34RT5110
www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. All parameters are ensured by test,
statistical analysis, or design unless otherwise specified
(1)
.
Symbol Parameter Condition Min Typ Max Units
Power
EN = H, Device Enabled
PRBS15 pattern,
1100 1250 mW
fCLK=340 MHz
RT= 50Ω to AV
CC
, Figure 2
Power Supply
P
Consumption
EN = L, Standby Mode
PRBS15 pattern,
850 1000 mW
fCLK=340 MHz
RT= 50Ω to AV
CC
, Figure 2
LVCMOS / LVTTL DC Specifications
High Level Input
VIH 2 V
DD
V
Voltage
Low Level Input
VIL GND 0.8 V
Voltage
High Level Output
VOH IOH = -3 mA 2.4 V
Voltage
Low Level Output
VOL IOL = 3 mA 0.4 V
Voltage
VIN = V
DD
, EQ2, EQ1, EQ0,
DE1, DE0, BYPASS, MODE 60 μA
IIH Input High Current
pins (pull down)
VIN = V
DD
, EN pin (pull up) -15 μA
VIN = 0 V, EQ2, EQ1, EQ0,
DE1, DE0, BYPASS, MODE 15 μA
IIL Input Low Current
pins (pull down)
VIN = 0 V, EN pin (pull up) -20 μA
Signal Detect
Default Input signal level to
Signal Detect High 80 mVp-p
SDH assert SD pin
Default Input signal level to
Signal Detect Low 20 mVp-p
SDL deassert SD
CML Inputs
VTX Input Voltage
Measured differentially at TPA,
Swing (Launch 800 1000 1560 mVp-p
Figure 1
(2)
Amplitude)
VICMDC DC-Coupled requirement
Input Common- Measured at TPB,
V
DD
-0.3 V
DD
-0.2 V
Mode Voltage VINmin = 800mV,
VINmax = 1200mV, Figure 1
VIN Measured differentially at TPB,
Input Voltage
Figure 1, 3.4 Gbps, Clock 150 1560 mVp-p
Sensitivity
Pattern
RIN Input resistance IN+ to V
DD
and IN- to V
DD
40 50 60 Ohms
Differential output
RLI 100 MHz – 1125 MHz 10 dB
return loss
CML Outputs
Measured DC outputs at TPC,
RT = 50Ω when DUT V
DD
is
Standby Output
VOFF off with OUT+ and OUT- AV
CC
- 10 AV
CC
+ 10 mV
Voltage
terminated by RT= 50Ω to
AV
CC
, Figure 2
(1) Typical parameters are measured at V
DD
= 3.3 V, T
A
= 25 °C. They are for reference purposes, and are not production-tested.
(2) Parameter is ensured by statistical analysis and/or design.
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