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DS34RT5110

www.ti.com

SNLS310G –MARCH 2009–REVISED APRIL 2013

DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis

Check for Samples: DS34RT5110

FEATURES

DESCRIPTION

The DS34RT5110 is a 10.2 Gbps (3 x 3.4 Gbps) high

• Optimized for HDMI/DVI Repeater Applications

performance re-clocking device that supports 3

• TMDS compatible Inputs with Configurable

Transition Minimized Differential Signaling (TMDS)

Receive Equalization Supporting Data Rates

data channels and a single clock channel over DVI™

up to 3.4 Gbps

v1.0, and HDMI™ v1.3a data rates up to 3.4 Gbps for

each data channel. The device incorporates a

• TMDS compatible Outputs with Configurable

configurable receive equalizer, a clock and data

Transmit De-Emphasis

recovery (CDR) circuit and a de-emphasis driver on

• Dedicated CDR on Each Data Channel

each data channel. The clock channel feeds a high-

Reduces Jitter Transfer, Enabling Multiple

performance phase-locked loop (PLL) that

Devices to be Cascaded without Impairing

regenerates a low jitter output clock for data recovery.

Signal Fidelity

The DS34RT5110 equalizes and retimes greater than

• Capable of Multi-Hop Extension of HDMI/DVI

25 meters 28 AWG of HDMI cable for 1080p

Applications at Data Rates between 250 Mbps

resolution with 12 bit deep color depth (2.25 Gbps), to

and 3.4 Gbps

a low jitter version of the clock and data signal

• Resistor Adjustable Differential Output Voltage

outputs, reducing both deterministic and random jitter.

Several devices can be cascaded for long links

for AC Coupled Cat5e and Cat6 Extension

without degrading signal fidelity. Obtaining total jitter

Applications

is 0.09 UI or less over the supported data rates. This

• 2 Equalizer Settings for a Wide Range of Cable

low level of output jitter provides system designers

Reaches at Different Data Rates

with extra margin and flexibility when working with

• Total Output Jitter of 0.09 UI at 2.25 Gbps

stringent timing budgets.

• Total Output Jitter of 0.10 UI at 3.4 Gbps

The transmitter supports configurable transmit de-

• DVI 1.0 and HDMI v1.3a Compatible TMDS

emphasis so the output can be optimized for driving

additional lengths of cables or FR4 traces.

Source and Sink Interface

• 7 mm x 7 mm 48 Pin WQFN Package

• >8 kV HBM ESD Protection

• 0 °C to +70 °C Operating Temperature

APPLICATIONS

• Repeater Applications

– Digital Routers

– HDMI / DVI Extender Multi-Hops

• Source Applications

– Video Cards

– Blu-ray DVD Players

– Game Consoles

• Sink Applications

– High Definition Displays

– Projectors

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis Check for Samples: DS34RT5110 FEATURES DESCRIPTION • • The DS34RT5110 is a 10.2 Gbps (3 x 3.4 Gbps) high performance re-clocking device that supports 3 Transition Minimized Differential Signaling (TMDS) data channels and a single clock channel over DVI™ v1.0, and HDMI™ v1.3a data rates up to 3.4 Gbps for each data channel.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com Application Diagram 5m 28 AWG DVI/HDMI Cable 10.2 G DVI/HDMI Source SER A/V Decoder 10.2 G DVI/HDMI Sink DES/Display Processor DS34RT5110 20m 28 AWG DVI/HDMI Cable 10.2 G DVI/HDMI Sink 10.2 G DVI/HDMI Source SER/A/V Decoder DS34RT5110 20m 28 AWG DVI/HDMI Cable 10.2 G DVI/HDMI Source SER/A/V Decoder DES/Display Processor 5m 28 AWG DVI/HDMI Cable DVI/HDMI Repeater 10.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Number I/O, Type LOCK Pin Name 14 O, LVCMOS Description VOD_CRL 48 I, Analog VOD control pin. Refer to Table 3. See Functional Description. External resistance = 24 kΩ to GND, Output DC Coupled Application. External resistance = 12 kΩ to GND, Output AC Coupled Application. LFp LFn 40 41 I, Analog Loop filter capacitor pins. See Functional Description.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage (VDD) -0.5V to 4.0 V LVCMOS Input Voltage -0.5V to (VDD+ 0.5) V LVCMOS Output Voltage -0.5V to (VDD+ 0.5) V CML Input/Output Voltage -0.5V to (VDD+ 0.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. All parameters are ensured by test, statistical analysis, or design unless otherwise specified (1).
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. All parameters are ensured by test, statistical analysis, or design unless otherwise specified(1). Symbol Parameter Condition Min Typ Max Units 800 1200 mVp-p AVCC- 0.35 AVCC- 0.20 V VO Differential Output voltage swing External resistor = 24 kΩ at VOD_CRL pin.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. All parameters are ensured by test, statistical analysis, or design unless otherwise specified(1). Symbol Parameter Condition Min Typ Max Units Clock Channel PLL Jitter Generation TROJ5 Total Output Jitter 25 MHz Clock Path, measured at TPC Figure 1 (7) (8) (9) 0.03 0.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com AVcc A 50Ö 50Ö B VOH = VDD Single-ended Waveforms @ A and B Vocm VOL = VDD - 500mV Vo = 1000 mVp-p Differential Waveform A-B 0V (DIFF) Figure 2. CML Output Swings at A/B (VOD_CRL = 24 kΩ) OUT+ 80% VO = (OUT+) ± (OUT-) 80% 0V 20% 20% OUTtR tF Figure 3. CML Output Transition Times IN 0V tDD, tCD OUT 0V Figure 4.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 SD 50% tSL 50% LOCK Figure 5. SD – LOCK Delay Time Functional Description The DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis consists of three data channels and a clock channel. Each data channel consists of a TMDS compatible receiver with a power efficient equalizer, a dedicated clock-data recovery (CDR) unit, and a TMDS compatible transmitter.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com PHASE-LOCKED-LOCKED LOOP (PLL) The clock channel has a high-performance PLL that creates a low jitter sampling clock for the clock and data recovery units in the data channels. An external loop filter, composed of 2.2 nF (+ 5% tolerance) capacitor and a 3.3 kΩ (+ 5% tolerance) resistor in series, are required between the LFp and the LFn pins.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 Table 3. VO Control External Resistor Value (VOD_CRL pin) Applications VO Level (mVp-p) 24 kΩ DC Coupled 1000 12 kΩ AC Coupled 1000 1-bit 1 to N bits 1-bit 1 to N bits 0 dB -3 dB -6 dB VO -9 dB VODE3 0V VODE2 VODE1 Figure 7.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com AUTOMATIC ENABLE FEATURE During normal operation (i.e. BYPASS pin is LOW), the DS34RT5110 can be configured to automatically enter STANDBY mode, if the PLL of the DS34RT5110 is not locked. The STANDBY mode can be implemented by connecting the LOCK DETECT (LOCK) pin to the external (LVCMOS) Enable (EN) pin.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 MODE = 1 20m CAT5 Cable HDMI Source HOP 1 SER/A/V Decoder DS34RT5110 20m CAT5 Cable MODE = 1 HOP 2 DS34RT5110 20m CAT5 Cable MODE = 0 (Default) 20m CAT5 Cable HDMI Sink Final HOP DES / Display Processor DS34RT5110 Figure 9.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com MODE = 1 D0 D0 D1 D1 DS34RT5110 D2 D2 CLK MODE = 0 (Default) CLK CLK D3 D3 DS34RT5110 D4 D4 D5 D5 Figure 11. DVI/HDMI Dual Link Application DC AND AC COUPLED APPLICATIONS The DS34RT5110 is designed to support TMDS differential pairs with DC coupled transmission lines. It contains integrated termination resistors (50Ω), pulled up to VDD at the input stage, and open collector outputs for DVI / HDMI signaling.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 VDD DS34RT5110 Driver VDD 505 505 505 505 Zo 6225 6225 DS34RT5110 Receiver VOD_CRL VOD_CRL 12 k5 24 k5 Figure 13. AC Coupled Application CABLE SELECTION AND INTER-PAIR SKEW DVI v1.0 and HDMI v1.3a specify Inter-Pair Skew requirements for the system.
PAGE 16
DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The TMDS differential inputs and outputs must have a controlled differential impedance of 100 Ω. It is preferable to route TMDS lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 Typical Performance Characteristics as a Repeater Pattern Generator DS34RT5110 Cable A Coax TPA TPB Cable B TPC Coax Jitter Test Instrument TPD Figure 16. Simplified Test Setup as a Single Repeater Figure 17. System Source Eye Diagram at TPA (3.4 Gbps) Figure 18. Device Sink Eye Diagram at TPB (3.4 Gbps, Cable A = 20m 28 AWG HDMI) Figure 19. Device Source Eye Diagram at TPC (3.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics as a Repeater (continued) 18 Figure 23. Device Sink Eye Diagram at TPB (2.25 Gbps, Cable A = 25m 28 AWG HDMI) Figure 24. Device Source Eye Diagram at TPC (2.25 Gbps, Cable A = 25m 28 AWG HDMI, EQ = 0x05, BYPASS = 0, DE = 0dB) Figure 25. Device Source Eye Diagram at TPC (2.25 Gbps, Cable A = 25m 28 AWG HDMI, EQ = 0x05, BYPASS = 0, DE = -3dB) Figure 26. System Sink Eye Diagram at TPD (2.
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DS34RT5110 www.ti.com SNLS310G – MARCH 2009 – REVISED APRIL 2013 Typical Performance Characteristics as a Repeater (continued) Figure 29. Device Source Eye Diagram at TPC (1.65 Gbps, Cable A = 35m 28 AWG HDMI, EQ = 0x05, BYPASS = 0, DE = 0dB) Figure 30. Device Source Eye Diagram at TPC (1.65 Gbps, Cable A = 35m 28 AWG HDMI, EQ = 0x05, BYPASS = 0, DE = -6dB) Figure 31. System Sink Eye Diagram at TPD (1.
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DS34RT5110 SNLS310G – MARCH 2009 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision F (April 2013) to Revision G • 20 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS34RT5110SQ/NOPB WQFN RHS 48 DS34RT5110SQE/NOPB WQFN RHS DS34RT5110SQX/NOPB WQFN RHS SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS34RT5110SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS34RT5110SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS34RT5110SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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