Datasheet

DS32EL0421, DS32ELX0421
SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com
LVDS Timing Specifications (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2)
Symbol Parameter Conditions Min Typ Max Units
t
CIT
TxCLKIN Transition Time See Figure 2 0.5 1.0 3.0 ns
See
(3)
t
XIT
TxIN Transition Time 0.15 3 ns
t
CIH
TxCLKIN High Time See Figure 3 0.7T T 1.3T ns
t
CIL
TxCLKIN Low Time 0.7T T 1.3T ns
t
STC
TxIN Setup to TxCLKIN -550 ps
t
HTC
TxIN Hold to TxCLKIN 900 ps
t
LVDLS
LVDS Input Clock Delay Step Size Programmable through the SMBus, 100 ps
register 30'h
Default setting = 011'b [7:5]
(3) Parameter is ensured by characterization and is not tested at production.
CML Electrical Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2) (3)
Symbol Parameter Conditions Min Typ Max Units
R
OT
Output Terminations On chip termination from TxOUT0/1 + 40 50 60 Ω
and TxOUT0/1 - to V
DD25
50Ω mode
75Ω mode 60 75 90 Ω
ΔR
OT
Mismatch in Output Termination Resistors 5 %
V
OD
Output Differential Voltage Swing Based on VOD_CTRL = 9.1 kΩ 1175 1350 1450 mV
P-P
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except V
OD
and ΔV
OD
.
(3) Typical values represent most likely parametric norms for V
CC
= +3.3V and T
A
= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
CML Timing Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2)
Symbol Parameter Conditions Min Typ Max Units
LR Line Rate Tested with alternating 1-0 pattern. 1.25 3.125 Gbps
t
OS
Output Overshoot See
(3)
10 %
t
R
Differential Low to High Transition Time See
(3)
60 90 ps
t
F
Differential High to Low Transition Time 60 90 ps
t
RFMM
Mismatch in Rise/Fall Time See
(3)
15 ps
t
DE
De-emphasis width Measured from zero-crossing at rising 1 UI
edge to 80% of VOD from zero-
crossing at falling edge. TDE is
measured at the High setting during
test.
t
BIT
Serializer Bit Width 0.2 x ns
t
CIP
t
SD
Serializer Propagation Delay – Latency Depends on mode — see Table 3 (10 – ns
14) T+
5.5
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms for V
CC
= +3.3V and T
A
= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(3) Parameter is ensured by characterization and is not tested at production.
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