Datasheet

DS32EL0421, DS32ELX0421
SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com
PIN DESCRIPTIONS (continued)
Pin Name Pin Number I/O, Type Description
LVDS Parallel Data Bus
TxCLKIN+ 37 I, LVDS Serializer input clock. TxCLKIN+/- are the inverting and non-inverting LVDS transmit clock input
TxCLKIN- 38 pins.
TxIN[4:0]+/- 39, 40, I, LVDS Serializer input data. TxIN[4:0]+/- are the inverting and non-inverting LVDS serializer input data
41, 42, pins.
43, 44,
45, 46,
47, 48
LVCMOS Control Pins
DC_B 5 I, DC-balance and Remote Sense pins. See Device Configuration section DEVICE
RS 6 LVCMOS CONFIGURATION for device behavior.
DE_EMPH0 9 I, DE_EMPH0, DE_EMPH1 select the output de-emphasis level. These pins are internally pull-
DE_EMPH1 10 LVCMOS down.
00: Off
01: Low
10: Medium
11: Maximum
TXOUT1_EN 12 I, DS32ELX0421 ONLY. When held high, redundant output TxOUT1+/- is enabled. This pin must
LVCMOS be tied high when using TxOUT1+/-.
RESET 30 I, When held low, reset the device.
LVCMOS 0 = Device Reset
1 = Normal operation
LOCK 31 O, Lock indication output. The input data on TxIN[0:4]+/- pins is ignored when LOCK pin is high.
LVCMOS
SMBus Interface
SCK 33 I/O, SMBus compatible clock.
SMBus
SDA 32 I/O, SMBus compatible data line.
SMBus
SMB_CS 34 I, SMBus SMBus chip select. When held high, SMBus management control is enabled.
Other
GPIO0 3 I/O, Software configurable I/O pin.
LVCMOS
GPIO1 4 I/O, Software configurable I/O pin.
LVCMOS
GPIO2 11 I/O, Software configurable I/O pin.
LVCMOS
NC 2, 8, 12, 13, Misc. No Connect, for DS32EL0421
19, 20, 21,
22, 23, 24,
29
2, 8, 13, 21, Misc. No Connect, for DS32ELX0421
22, 23, 24,
29
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS32EL0421 DS32ELX0421