Datasheet
DS32EL0421, DS32ELX0421
SNLS282F –MAY 2008–REVISED APRIL 2013
www.ti.com
Addr Name Bits Field R/W Default Description
(Hex)
2B Event Config 7 Reserved 0
6 PLL Lock Event R/W 0 0: Count PLL lock events
1: Do not count PLL lock events
5 Link Event R/W 0 0: Count link events
1: Do not count link events
4 Loss of Signal R/W 0 0: Count loss of signal events
Event 1: Do not count loss of signal events
3 Event Count R/W 0 0: Select PLL event count for reading
Select 1: Select link event count for reading
2 Clear PLL Error R/W 0 1: Reset PLL error count. Self clearing bit.
Count
1 Clear Link Error R/W 0 1: Reset link error count. Self clearing bit.
Count
0 Enable Count R/W 0 0: Disable event counters
1: Enable event counters
2C Event Count 7:0 Event Counter R 0
2D Reserved
2E Analog Driver 7 Reserved 0
6 Reverse Data R/W 0 0: Normal
Order 1: Reverse output data order
5:2 Reserved R/W 0
1 Link Detect 1 R/W 0 Link detect value for channel 1
0 Link Detect 0 R/W 0 Link detect value for channel 0
2F Tx Config 7:6 Reserved 0
5 Output R/W 1'b 0: 75 Ω terminations
Termination 1: 50 Ω terminations
4 Link Start R/W 1'b 0: Start when TxOUT0 or TxOUT1 link
1: Start when TxOUT0 and TxOUT1 linke
3 Link Stop R/W 1'b 0: Stop when TxOUT0 and TxOUT1 both links invalid
1: Stop when TxOUT0 or TxOUT1 break link, either link is
invalid
2 TxOUT Override R/W 0 0: TxOUT0 enabled by default, TxOUT1_en pin controls
channel1
1: Override enable of TxOUT0 and TxOUT1
1 TxOUT1 Enable R/W 0 0: TxOUT1 disabled
1: TxOUT1 enabled
For proper operation of TxOUT1, the TxOUT1_EN pin
must be held high.
0 TxOOUT0 Enable R/W 0 0: TxOUT0 disabled
1: TxOUT0 enabled
30 Clock Delay 7:5 TxCLKIN Delay R/W 011’b 000: Min clock delay, 350 ps
011: 725 ps
111: Max clock delay, 1225 ps
4:0 Reserved 00010’b
31–68 Reserved
69 Output Amplitude 7:3 Reserved 0
Adjust
2:0 Amplitude Adjust R/W 011’b 000: Level 7
001: Level 8 (Highest output)
010: Level 5
011: Level 6 (Normal output)
100: Level 4
101: Level 3
110: Level 2
111: Level 1 (Lowest output)
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