Datasheet

DS32EL0421, DS32ELX0421
www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013
Addr Name Bits Field R/W Default Description
(Hex)
26 Power Down 7 Channel Reset R/W 0 1: Reset high speed channel. Self-clearing bit.
6 Clock Powerdown R/W 0 1: Power down parallel, parallel-to-serial, and always on
clock
5 LVDS Clock R/W 1'b 0: Disable TxCLKIN
enable 1: Enable TxCLKIN
4 TxIN4 Enable R/W 1'b 0: Disable TxIN4
1: Enable TxIN4
3 TxIN3 Enable R/W 1'b 0: Disable TxIN3
1: Enable TxIN3
2 TxIN2 Enable R/W 1'b 0: Disable TxIN2
1: Enable TxIN2
1 TxIN1 Enable R/W 1'b 0: Disable TxIN1
1: Enable TxIN1
0 TxIN0 Enable R/W 1'b 0: Disable TxIN0
1: Enable TxIN0
27 Event Disable 7:5 Reserved R/W 0
4 PLL Lock Disable R/W 0 0: Count clock errors
1: Clock error count disabled
3 FIFO Error R/W 0 0: Count FIFO erros 1: FIFO error count disabled
Disable
2 Parallel Clock R/W 0 0: Count clock detect errors
Detect Disable 1: Clock detect count disabled
1 Clock Loss of R/W 0 0: Count clock los of signal errors
Signal Disable 1: Clock loss of signal count disabled
0 Data Loss of R/W 0 0: Count data los of signal errors
Signal Disable 1: Clock data of signal count disabled
28 LVDS Operation 7:2 Reserved 0
1 LVDS Loss of R/W 0 1: Preset signal for LVDS loss of signal register
Signal Preset
0 LVDS Loss of R/W 0 1: Clear signal for LVDS loss of signal register
Signal Reset
29 Loss of Signal 7:6 Reserved 0
Status
5 Clock Loss of R 0 0: Clock present
Signal 1: No clock present on TxCLKIN
4:0 Data Loss of R 0 0: Data present
Signal 1: No data present on TxIN4:0
2A Event Status 7:4 Reserved 0
3 TxCLKIN Detect R/W 0 0: TxCLKIN not detected
1: TxCLKIN detected
2 Reserved 0
1:0 Link Detect 1:0 R/W 0 0: Link not detected
1: Link detected
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