Datasheet

DS32EL0421, DS32ELX0421
SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com
Addr Name Bits Field R/W Default Description
(Hex)
05 GP In 7:3 Reserved 0
2 GP In 2 R 0 Input value on GPIO2
1 GP In 1 R 0 Input value on GPIO1
0 GP In 0 R 0 Input value on GPIO0
06 GP Out 7:3 Reserved 0
2 GP Out 2 R/W 0 Output value on GPIO2
1 GP Out 1 R/W 0 Output value on GPIO1
0 GP Out 0 R/W 0 Output value on GPIO0
07–1F Reserved
20 De-Emphasis 7:3 Reserved 0
2 Pin Override R/W 0 0: Pin values determine setting
1: Register overrides pin values
1:0 De-emphasis R/W 0 00: No de-emphasis
level 01: Low
10: Medium
11: High
21 Device Config 7 NRZI enable R/W 0 1: Enable NRZI, if override bit is set
6 DV disable R/W 0 1: Disable Data Valid
5 Reserved R/W 0
4 Scrambler Enable R/W 0 1: Scrambler enable, requires override bit to change
setting
3 DC Bal encoder R/W 0 1: Bypass encoder, requires override bit to change setting
bypass
2 Training R/W 0 1: Enable training sequence, requires override bit to
Sequence Enable change setting
1:0 Device R/W 0 MSB: Remote Sense enable, active low
Configuration LSB: DC balance encoder enable, active low
Requires override bit to change settings through registers.
Normally controlled by pins. See Table 2 for more
information.
22 Device Config 7:5 Reserved 0
Override
4 NRZ bypass R/W 0 1: Unlock reg 21’h bit 7
override
3 Scrambler bypass R/W 0 1: Unlock reg 21’h bit 4
override
2 DC Bal encoder R/W 0 1: Unlock reg 21’h bit 3
bypass override
1 Training R/W 0 1: Unlock reg 21’h bit 2
sequence enable
override
0 Config pin R/W 0 1: Unlock reg 21’h bits 1 and 0
override
23 Reserved
24 LVDS Clock Delay 7 TxCLKIN Delay R/W 0 0: TxCLKIN delay enable
Enable Bypass 1: Bypass TxCLKIN delay
6:0 Reserved 0
25 Reserved
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Product Folder Links: DS32EL0421 DS32ELX0421