Datasheet

DS32EL0421, DS32ELX0421
SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com
Typical Performance Characteristics
The eye diagrams shown below illustrate the typical performace of the DS32ELX0421/DS32EL0421 configured with RS =
0,DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used
an LMK03000C to generate the various clock frequencies.
Figure 12. CML Serial Differential Output 1.25 Gbps Figure 13. CML Serial Differential Output 3.125 Gbps
Figure 14. CML Serial Singled Ended Output (+) 1.25 Gbps Figure 15. CML Serial Single Ended Output (+) 3.125 Gbps
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