Datasheet

DS32EL0421, DS32ELX0421
SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com
PROPAGATION DELAY
Once the serializer is locked, the amount of time it takes for a bit to travel into the device through the DDR LVDS
inputs and out through the CML serial output is defined to be the propagation delay. The propagation delay
through the DS32EL0421/DS32ELX0421 due to the analog circuitry is considered negligible compared to the
time delay caused by the digital components. The information presented in this section allows system designers
to predict the propagation delay through the device in terms of clock cycles which are proportional to the high
speed serial line rate.
Each clock cycle shown in Table 3 is defined to be 1/2 t
CIP
. Note at 3.125Gbps, t
CIP
is 312.5MHz, T is 1/2 tCIP or
156.25MHz which is 6.40ns per clock..
Table 3. Serializer Propagation Delay
Config. Pins LVDS DC Balance Scrambler NRZ CML Analog Total
(DC_B, RS) Interface Encoder Encoder interface Delay Propagation
Delay
Data Flow (left to right)
0, 0 3 clocks 1 clock – – 5 – 6 clocks 2 clocks 11 – 12 clocks
+ ~5.5ns + ~5.5ns
0, 1 3 clocks 1 clock 1 clock 1 clock 5 – 6 clocks 2 clocks 13 – 14 clocks
+ ~5.5ns + ~5.5ns
1, 0 3 clocks – 1 clock 1 clock 5 – 6 clocks 2 clocks 12 – 13 clocks
+ ~5.5ns + ~5.5ns
1, 1 3 clocks – – – 5 – 6 clocks 2 clocks 10 – 11 clocks
+ ~5.5ns + ~5.5ns
Application Information
GPIO PINS
The GPIO pins can be useful tools when debugging or evaluating the system. For specific GPIO configurations
and functions refer to registers 2, 3, 4, 5 and 6 in the device register map.
GPIO pins are commonly used when there are multiple serializers on the same SMBus. In order to program
individual settings into each serializer, they will each need to have a unique SMBus address. To reprogram
multiple serializers on a single SMBus, configure the first serializer such that the SMBus lines are connected to
the FPGA or host controller. The CS pin of the second serializer should be tied to GPIO0 of the first serializer,
with the CS pin of the next serializer tied to GPIO0 of its preceding serializer. By holding all of the GPIO0 pins
low, the first serializer’s address may now be reprogrammed by writing to register 0. The first serializer’s GPIO
pin can now be asserted and the second serializer’s address may now be reprogrammed.
HIGH SPEED COMMUNICATION MEDIA
Using the serializer’s integrated de-emphasis blocks in combination with the DS32EL0124 or DS32ELX0124’s
integrated equalization blocks allows data to be transmitted across a variety of media at high speeds. Factors
that can limit device performance include excessive input clock jitter, noisy power rails, EMI from nearby noisy
components and poor layout techniques. Although many cables contain wires of similar gauge and shielding,
performance can vary greatly depending on the quality of the connector.
REDUNDANCY APPLICATIONS
The DS32ELX0421 has two high speed CML serial outputs. SMBus register control allows the device to use a
single output exclusively, or both outputs simultaneously. This allows a single serializer to transmit data to two
independant receiving systems, a primary and secondary endpoint. Some applications require a redundancy
measure in case the primary signal path is compromised. The secondary output can be activated “on-the-go”, if a
problem is detected on the primary link. See the Redundancy / Fail Over Configuration section located under
Register Recipes.
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