Datasheet

DS32EL0421, DS32ELX0421

SNLS282F –MAY 2008–REVISED APRIL 2013

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Table 1. De-Emphasis Control Table

DE_EMPH[1:0] Output De-Emphasis Level

00'b Off

01'b Low

10'b Medium

11'b High

The DS32ELX0421 provides a secondary serial output, supporting redundancy applications. The redundant

output driver can be enabled by setting TXOUT1_EN pin to HIGH or by activating it through the SMBus reigsters.

DEVICE CONFIGURATION

There are four ways to configure the DS32EL0421 and DS32ELX0421 serializers, these combinations are shown

in Table 2. Refer to Figure 7 to see how the combinations of the RS and DC_B pins change the link startup

behavior of the serializers. When connecting to a deserializer other than the DS32EL0124 or DS32ELX0124,

Remote Sense should be disabled. The scrambler and NRZI encoder shown in Table 2 can be enabled or

disabled through register programming.

When Remote Sense is enabled, with RS pin tied low, the serializer must be connected directly to a

DS32EL0124 or DS32ELX0124 deserializer without any active components between them. The Remote Sense

module features an upstream communication method for the serializer and deserializer to communicate. This

feature is used to pass link status information between the 2 devices. When Remote Sense is enabled the

serializer will send a training pattern to the deserializer to establish lock and lane alignment.

If DC-Balance is enabled, a maximum of 4 parallel LVDS lanes can be used to receive data. The fifth lane

(TXIN4±) is used for Data Valid signaling. Each time a serializer establishes a link to a deserializer with DC-

Balance enabled and Remote Sense disabled, the Data Valid input to the serializer must be held high for 110

LVDS clock periods. If the Data Valid input to the serializer is logic HIGH, then SYNC characters are transmitted.

If the deserializer receives a SYNC character, then the LVDS data outputs will all be logic low and the Data Valid

output will be logic high. If the deserializer detects a DC-Balance code error, the output data pins will be set to

logic high with the Data Valid output also set to logic high.

In the case where DC-Balance is enabled and Remote Sense is disabled, with RS set to high and DC_B set to

low, it is recommended that the host device periodically toggle the Data Valid input to the serializer, to transmit

SYNC symbols on the line, to ensure that the deserializer is and remains locked. In this configuration the

deserializer or receiving device does not have a way to directly notify the serializer if it has lost lock. Periodically

sending SYNC symbols will allow the receiving system to reacquire lock if a problem has occurred. With these

pin settings the DS32EL0421/DS32ELX0421 and DS32EL0124/DS32ELX0124 devices can interface with other

active component in the high speed signal path, such as fiber modules.

When both Remote Sense and DC-Balance are disabled, RS and DC_B pins set to high, the LVDS lane

alignment is not maintained. In this configuration, data formatting is handled by an FPGA or external source. This

pin setting combination also allows for the DS32EL0421/DS32ELX0421 devices to interface with active

components other than the DS32EL0124/DS32ELX0124 in the high speed signal path. In this configuration the

host device is responsible for DC balancing the data in an AC coupled application.

Product Folder Links: DS32EL0421 DS32ELX0421