Datasheet

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DS32EL0421, DS32ELX0421

www.ti.com

SNLS282F –MAY 2008–REVISED APRIL 2013

DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS

Parallel Interface

Check for Samples: DS32EL0421, DS32ELX0421

FEATURES

DESCRIPTION

The DS32EL0421/DS32ELX0421 is a 125 MHz to

• 5-bit DDR LVDS Parallel Data Interface

312.5 MHz (DDR) serializer for high-speed serial

• Programmable Transmit De-emphasis

transmission over FR-4 printed circuit board

• Configurable Output Levels (V

)

backplanes, balanced cables, and optical fiber. This

easy-to-use chipset integrates advanced signal and

• Selectable DC-balanced Encoder

clock conditioning functions, with an FPGA friendly

• Selectable Data Scrambler

interface.

• Remote Sense for Automatic Detection and

The DS32EL0421/DS32ELX0421 serializes up to 5

Negotiation of Link Status

parallel input LVDS channels to create a maximum

• On Chip LC VCOs

data payload of 3.125 Gbps. If the integrated DC-

• Redundant Serial Output (ELX device only)

balance encoding is enabled, the maximum data

payload achievable is 2.5 Gbps.

• Data Valid Signaling to Assist with

Synchronization of Multiple Receivers

The DS32EL0421/DS32ELX0421 serializers feature

remote sense capability to automatically detect and

• Supports AC- and DC-coupled Signaling

negotiate link status with its companion

• Integrated CML and LVDS Terminations

DS32EL0124/DS32ELX0124 deserializers without

• Configurable PLL Loop Bandwidth

requiring an additional feedback path.

• Programmable Output Termination (50Ω or

The parallel LVDS interface reduces FPGA I/O pins,

75Ω).

board trace count and alleviates EMI issues, when

• Built-in Test Pattern Generator

compared to traditional single-ended wide bus

interfaces.

• Loss of Lock and Error Reporting

• Configurable via SMBus

The DS32EL0421/DS32ELX0421 is programmable

through a SMBus interface as well as through control

• 48-pin WQFN Package with Exposed DAP

pins.

TARGET APPLICATIONS

• Imaging: Industrial, Medical Security, Printers

• Displays: LED Walls, Commercial

• Video Transport

• Communication Systems

• Test and Measurement

• Industrial Bus

KEY SPECIFICATIONS

• 1.25 to 3.125 Gbps Serial Data Rate

• 125 to 312.5 MHz DDR Parallel Clock

• -40° to +85°C Temperature Range

• >8 kV ESD (HBM) Protection

• Low Intrinsic Jitter — 35ps at 3.125 Gbps

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface Check for Samples: DS32EL0421, DS32ELX0421 FEATURES DESCRIPTION • • • • • • The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Application DS32ELX0421 5 LVDS R0 D1 R1 Redundant Driver Redundant Link Retimed Output LVDS Interface D0 Serial to Parallel Parallel to Serial Encoder LVDS Interface LVDS Interface LVDS Interface LVDS Interface 3.
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DS32EL0421, DS32ELX0421 VDD33 1 N/C 2 TXIN4- TXIN4+ TXIN3- TXIN3+ TXIN2- TXIN2+ TXIN1- TXIN1+ TXIN0- TXIN0+ TXCLKIN- TXCLKIN+ 47 46 45 44 43 42 41 40 39 38 37 SNLS282F – MAY 2008 – REVISED APRIL 2013 48 www.ti.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O, Type Description 37 38 I, LVDS Serializer input clock. TxCLKIN+/- are the inverting and non-inverting LVDS transmit clock input pins. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48 I, LVDS Serializer input data. TxIN[4:0]+/- are the inverting and non-inverting LVDS serializer input data pins.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (3.3V VDD33) −0.3V to +3V Supply Voltage (2.5V VDD25) LVCMOS Input Voltage −0.3V to (VDD + 0.3V) LVCMOS Output Voltage −0.3V to (VDD + 0.3V) LVDS Input Voltage (IN+, IN-) −0.3V to +3.6V CML Output Voltage −0.3V to +3.6V Junction Temperature +125°C Storage Temperature Range -65°C to +150°C Lead Temperature Range Soldering (4 sec.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Power Supply Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol PD Parameter Condition Power Consumption 1 Output Enabled Power Consumption 2 Output Enabled Min Typ Max 1.25 Gbps 460 540 2.5 Gbps 485 560 3.125 Gbps 500 575 1.25 Gbps 580 670 2.5 Gbps 605 695 3.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 SMBus Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter (1) (2) Conditions Min Typ Max Units 100 kHz tSMB Bus Operating Frequency 10 tBUF Bus Free Time between Stop and Start Condition 4.7 μs tHD:STA Hold time after (repeated) start condition. After this period, the first clock is generated. 4.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com LVDS Timing Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol Parameter tCIT TxCLKIN Transition Time tXIT TxIN Transition Time tCIH TxCLKIN High Time tCIL Conditions See Figure 2 See (3) Min Typ Max Units 0.5 1.0 3.0 ns 3 ns 0.15 0.7T T 1.3T ns TxCLKIN Low Time 0.7T T 1.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 CML Timing Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com tCIP/2 +100 mV TXCLK 0V -100 mV tCIL, tCIH tSTC tHTC Hold Setup TXn 0V Figure 3. Serializer (LVDS Interface) Setup/Hold and High/Low Times tCIP/2 TxCLKIN Clock Delay (Programmable) Programmable Delay Clock (Internal) tHTC tSTC TxIN Valid Data Window Figure 4.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Previous Cycle Current Cycle Next Cycle Input Transmit Clock LVDS Data-0 A0 A1 A2 A3 LVDS Data-1 B0 B1 B2 B3 LVDS Data-2 C0 C1 C2 C3 LVDS Data-3 D0 D1 D2 D3 LVDS Data-4 E0 E1 E2 E3 Last Bit Out First Bit Out E3 D3 B3 C3 A3 E2 D2 B2 C2 A2 E1 D1 B1 C1 A1 E0 D0 B0 C0 A0 Serialized CML Output Figure 6.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com LVDS INPUTS The DS32EL0421 and DS32ELX0421 have standard 2.5V LVDS inputs which are compliant with ANSI/TIA/EIA644. These inputs have internal 100Ω termination resistors. It is recommended that the PCB trace between the FPGA and the serializer be less than 40-inches. Longer PCB traces may degrade the quality of the input signal.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Power-On/Reset TxCLKIN does not exist IDLE RS: 1, DC_B: 0 RS: 1, DC_B: 1 TxCLKIN exist LINK DETECT Link Detect fail LINK ACQUISITION NORMAL Figure 7. Serializer State Diagram SCRAMBLER and NRZI Encoder The CDR of the DS32EL0124 and the DS32ELX0124 expect a transition density of 20% for a period of 200 μs.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Table 1. De-Emphasis Control Table DE_EMPH[1:0] Output De-Emphasis Level 00'b Off 01'b Low 10'b Medium 11'b High The DS32ELX0421 provides a secondary serial output, supporting redundancy applications. The redundant output driver can be enabled by setting TXOUT1_EN pin to HIGH or by activating it through the SMBus reigsters.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Table 2.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 6. 7. 8. 9. The The The The www.ti.com Host drive the 8-bit data byte. Device drives an ACK bit (“0”). Host drives a STOP condition. Host de-selects the device by driving its SMBus CS signal Low. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Reading a Register To read a register, the following protocol is used (see SMBus 2.0 specification). 1.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 SMBus Device FPGA Host 3V3 SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 Figure 8. SMBus Configuration 1 SMBus Device FPGA Host SMBus Device SMBus Device SMB_CS SDA SCK SMB_CS SDA SCK SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 Figure 9.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com PROPAGATION DELAY Once the serializer is locked, the amount of time it takes for a bit to travel into the device through the DDR LVDS inputs and out through the CML serial output is defined to be the propagation delay. The propagation delay through the DS32EL0421/DS32ELX0421 due to the analog circuitry is considered negligible compared to the time delay caused by the digital components.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 LINK AGGREGATION Multiple DS32EL0421/DS32ELX0421 serializers and D32EL0124/DS32ELX0124 deserializers can be aggregated together if an application requires a data throughput of more than 3.125 Gbps. By utilizing the data valid signal of each device, the system can be properly deskewed to allow for a single cable, such as CAT-6, DVI-D, or HDMI, to carry data payloads beyond 3.125 Gbps.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics The eye diagrams shown below illustrate the typical performace of the DS32ELX0421/DS32EL0421 configured with RS = 0,DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an LMK03000C to generate the various clock frequencies. 20 Figure 12. CML Serial Differential Output 1.25 Gbps Figure 13. CML Serial Differential Output 3.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Register Map The register information for the serializer is shown in the table below. Some registers have been omitted or marked as reserved; these are for internal testing and should not be written to. Some register bits require an override bit to be set before they can be written to.
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DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 Addr (Hex) Name 05 GP In 06 GP Out Bits www.ti.
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DS32EL0421, DS32ELX0421 www.ti.com Addr (Hex) 26 27 28 29 2A SNLS282F – MAY 2008 – REVISED APRIL 2013 Name Power Down Event Disable LVDS Operation Loss of Signal Status Event Status Bits Field R/W Default Description 7 Channel Reset R/W 0 1: Reset high speed channel. Self-clearing bit.
PAGE 24
DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 Addr (Hex) Name 2B Event Config Bits www.ti.
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DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Register Recipes Many features of the serializer contained within the SMBus registers require multiple writes to configure and enable. This methodology was implemented to prevent accidental register writes from causing undesired device behavior. Several recipes for common features are listed below. When experimenting with other SMBus register features, be sure to read through the register map for override and enable bits.
PAGE 26
DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision E (April 2013) to Revision F • 26 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS32EL0421SQ/NOPB WQFN RHS 48 DS32EL0421SQE/NOPB WQFN RHS DS32EL0421SQX/NOPB WQFN RHS DS32ELX0421SQ/NOPB WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS32EL0421SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS32EL0421SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS32EL0421SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS32ELX0421SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS32ELX0421SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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