Datasheet
VDD33 1
LT_EN 2
GPIO0 3
GPIO1 4
5
6
7
8
9
10
11
12
DC_B
RS
VDD25
N/C
N/C
N/C
GPIO2
RX_MUX_SEL
VDD3336
VDD2535
SMB_CS34
SCK33
32
31
30
29
28
27
26
25
SDA
LOCK
RESET
N/C
VDDPLL
LF_CP
LF_REF
VDD25
RXOUT4-48
RXOUT4+47
RXOUT3-46
RXOUT3+45
44
43
42
41
40
39
38
37
RXOUT2-
RXOUT2+
RXOUT1-
RXOUT1+
RXOUT0-
RXOUT0+
RXCLKOUT-
RXCLKOUT+
N/C 24
N/C 23
TXOUT- 22
TXOUT+ 21
20
19
18
17
16
15
14
13
RXIN1-
RXIN1+
VDD33
RXIN0-
RXIN0+
VDD33
VOD_CTRL
N/C
49 DAP = GND
DS32ELX0124
DS32EL0124, DS32ELX0124
www.ti.com
SNLS284K –MAY 2008–REVISED APRIL 2013
Figure 2. WQFN Package
Package Number RHS0048A
PIN DESCRIPTIONS
Pin Name Pin Number I/O, Type Description
VDD33 1, 15, 18, 36 I, VDD 3.3V supply
VDD25 7, 25, 35 I, VDD 2.5V supply
VDD_PLL 28 I, VDD 3.3V supply
LF_CP 27 Analog Loop filter capacitor connection
LF_REF 26 Analog Loop filter ground reference
Exposed Pad 49 GND Exposed Pad must be connected to GND by 9 vias.
CML I/O
RxIN0+ 16 I, CML Non-inverting and inverting high speed CML differential inputs of the
RxIN0- 17 deserializer. These inputs are internally terminated.
RxIN1+ 19 I, CML DS32ELX0124 only. Non-inverting and inverting high speed CML
RxIN1- 20 differential inputs of the deserializer. These inputs are internally terminated.
TxOUT+ 21 O, CML DS32ELX0124 only. Retimed serialized high speed output. Non-inverting
TxOUT- 22 and inverting speed CML differential outputs of the deserializer. These
outputs are internally terminated.
LVDS Parallel Data Bus
RxCLKOUT+ 37 O, LVDS Deserializer output clock. RxCLKOUT+/- are the non-inverting and inverting
RxCLKOUT- 38 LVDS recovered clock output pins.
RxOUT[0:4]+/- 39, 40, 41, 42, 43, 44, 45, O, LVDS Deserializer output data. RxOUT[0:4]+/- are the non-inverting and inverting
46, 47, 48 LVDS deserialized output data pins.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS32EL0124 DS32ELX0124